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Searched refs:AMDGPU (Results 1 – 25 of 113) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp116 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
203 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
204 AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1), in getInstrAlternativeMappings()
205 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
206 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
207 AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1)}), in getInstrAlternativeMappings()
306 AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID; in getDefaultMappingVOP()
478 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
561 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
566 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64); in getInstrMapping()
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H A DSIRegisterInfo.cpp1400 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1401 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in getRegSplitParts()
1402 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in getRegSplitParts()
1403 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in getRegSplitParts()
1407 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1408 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in getRegSplitParts()
1412 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1416 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, in getRegSplitParts()
1420 AMDGPU::sub0, AMDGPU::sub1, in getRegSplitParts()
1451 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7 in getRegSplitParts()
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H A DSIInstrInfo.cpp1892 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
1893 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in insertSelect()
1894 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in insertSelect()
1895 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in insertSelect()
1899 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in insertSelect()
1900 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, in insertSelect()
1901 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, in insertSelect()
3192 case AMDGPU::COPY: return AMDGPU::COPY; in getVALUOp()
3193 case AMDGPU::PHI: return AMDGPU::PHI; in getVALUOp()
3195 case AMDGPU::WQM: return AMDGPU::WQM; in getVALUOp()
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H A DSIOptimizeExecMasking.cpp62 case AMDGPU::COPY: in isCopyFromExec()
63 case AMDGPU::S_MOV_B64: in isCopyFromExec()
77 case AMDGPU::COPY: in isCopyToExec()
95 case AMDGPU::S_AND_B64: in isLogicalOpOnExec()
96 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
97 case AMDGPU::S_XOR_B64: in isLogicalOpOnExec()
101 case AMDGPU::S_NOR_B64: in isLogicalOpOnExec()
117 case AMDGPU::S_AND_B64: in getSaveExecOp()
119 case AMDGPU::S_OR_B64: in getSaveExecOp()
121 case AMDGPU::S_XOR_B64: in getSaveExecOp()
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H A DSIFoldOperands.cpp146 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in isInlineConstantIfFolded()
152 AMDGPU::V_FMA_F32 : (IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16); in isInlineConstantIfFolded()
181 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) in updateOperand()
289 if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 || in tryAddToFoldList()
291 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) { in tryAddToFoldList()
295 AMDGPU::V_FMA_F32 : (IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16); in tryAddToFoldList()
609 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpc()
657 if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 || in tryConstantFoldOp()
664 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
668 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in tryConstantFoldOp()
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H A DSIPeepholeSDWA.cpp629 case AMDGPU::V_BFE_I32: in matchSDWAOperand()
880 assert((Opc == AMDGPU::V_ADD_I32_e64 || Opc == AMDGPU::V_SUB_I32_e64) && in pseudoOpConvertToVOP2()
992 SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode)); in convertToSDWA()
1005 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst) != -1); in convertToSDWA()
1009 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1012 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1021 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0) != -1 && in convertToSDWA()
1033 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1) != -1 && in convertToSDWA()
1051 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::clamp) != -1); in convertToSDWA()
1060 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) { in convertToSDWA()
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H A DSILoadStoreOptimizer.cpp970 return std::make_pair(AMDGPU::sub1, AMDGPU::sub0); in getSubRegIdxs()
972 return std::make_pair(AMDGPU::sub2, AMDGPU::sub0_sub1); in getSubRegIdxs()
974 return std::make_pair(AMDGPU::sub3, AMDGPU::sub0_sub1_sub2); in getSubRegIdxs()
981 return std::make_pair(AMDGPU::sub1_sub2, AMDGPU::sub0); in getSubRegIdxs()
983 return std::make_pair(AMDGPU::sub2_sub3, AMDGPU::sub0_sub1); in getSubRegIdxs()
990 return std::make_pair(AMDGPU::sub1_sub2_sub3, AMDGPU::sub0); in getSubRegIdxs()
1002 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1); in getSubRegIdxs()
1004 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1_sub2); in getSubRegIdxs()
1006 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1_sub2_sub3); in getSubRegIdxs()
1013 return std::make_pair(AMDGPU::sub0_sub1, AMDGPU::sub2); in getSubRegIdxs()
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H A DSIInsertSkips.cpp221 Opcode = AMDGPU::V_CMPX_O_F32_e64; in kill()
267 case AMDGPU::SI_KILL_I1_TERMINATOR: { in kill()
278 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC) in kill()
283 unsigned Opcode = KillVal ? AMDGPU::S_ANDN2_B64 : AMDGPU::S_AND_B64; in kill()
285 .addReg(AMDGPU::EXEC) in kill()
334 const unsigned CondReg = AMDGPU::VCC; in optimizeVccBranch()
368 unsigned SReg = AMDGPU::NoRegister; in optimizeVccBranch()
455 case AMDGPU::SI_MASK_BRANCH: in runOnMachineFunction()
460 case AMDGPU::S_BRANCH: in runOnMachineFunction()
512 case AMDGPU::S_CBRANCH_VCCZ: in runOnMachineFunction()
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H A DAMDGPURegisterInfo.cpp32 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, in getSubRegFromChannel()
33 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, in getSubRegFromChannel()
34 AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, in getSubRegFromChannel()
35 AMDGPU::sub15 in getSubRegFromChannel()
63 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
H A DGCNDPPCombine.cpp122 auto DPP32 = AMDGPU::getDPPOp32(Op); in getDPPOp()
126 auto E32 = AMDGPU::getVOPe32(Op); in getDPPOp()
141 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
143 case AMDGPU::COPY: in getOldOpndValue()
144 case AMDGPU::V_MOV_B32_e32: { in getOldOpndValue()
178 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
252 case AMDGPU::V_MAX_U32_e32: in foldOldOpnd()
256 case AMDGPU::V_MAX_I32_e32: in foldOldOpnd()
260 case AMDGPU::V_MIN_I32_e32: in foldOldOpnd()
265 case AMDGPU::V_MUL_I32_I24_e32: in foldOldOpnd()
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H A DSIOptimizeExecMaskingPreRA.cpp91 return AMDGPU::NoRegister; in getOrNonExecReg()
98 if (SavedExec == AMDGPU::NoRegister) in getOrExecSource()
138 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
144 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
154 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
161 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
168 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
173 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
180 return AMDGPU::NoRegister; in optimizeVcndVcmpPair()
231 DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI}); in runOnMachineFunction()
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H A DSIShrinkInstructions.cpp74 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
193 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
198 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
236 if (Opc == AMDGPU::S_AND_B32) { in shrinkScalarLogicOp()
242 Opc = AMDGPU::S_ANDN2_B32; in shrinkScalarLogicOp()
250 Opc = AMDGPU::S_ORN2_B32; in shrinkScalarLogicOp()
255 Opc = AMDGPU::S_XNOR_B32; in shrinkScalarLogicOp()
261 if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) && in shrinkScalarLogicOp()
558 AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32; in runOnMachineFunction()
631 if (DstReg != AMDGPU::VCC) in runOnMachineFunction()
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H A DSILowerControlFlow.cpp195 .addReg(AMDGPU::EXEC) in emitIf()
219 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64_term), AMDGPU::EXEC) in emitIf()
289 .addReg(AMDGPU::EXEC) in emitElse()
297 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC) in emitElse()
298 .addReg(AMDGPU::EXEC) in emitElse()
376 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64_term), AMDGPU::EXEC) in emitLoop()
398 BuildMI(MBB, InsPt, DL, TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC) in emitEndCf()
489 case AMDGPU::SI_IF: in runOnMachineFunction()
493 case AMDGPU::SI_ELSE: in runOnMachineFunction()
501 case AMDGPU::SI_LOOP: in runOnMachineFunction()
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H A DSIFrameLowering.cpp74 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO) in emitFlatScratchInit()
77 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI) in emitFlatScratchInit()
85 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO) in emitFlatScratchInit()
95 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI) in emitFlatScratchInit()
112 return AMDGPU::NoRegister; in getReservedPrivateSegmentBufferReg()
164 return std::make_pair(AMDGPU::NoRegister, AMDGPU::NoRegister); in getReservedPrivateSegmentWaveByteOffsetReg()
255 if (SPReg != AMDGPU::SP_REG) { in emitEntryFunctionPrologue()
401 GitPtrLo = AMDGPU::SGPR8; in emitEntryFunctionScratchSetup()
528 return AMDGPU::NoRegister; in findScratchNonCalleeSaveRegister()
624 if (StackPtrReg == AMDGPU::NoRegister) in emitEpilogue()
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H A DSIInsertWaitcnts.cpp362 AMDGPU::IsaVersion IV;
535 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr), in updateByEvent()
543 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0), in updateByEvent()
573 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
578 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
587 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
600 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
792 return (Opc == AMDGPU::S_CBRANCH_VCCNZ || Opc == AMDGPU::S_CBRANCH_VCCZ) && in readsVCCZ()
815 AMDGPU::Waitcnt Wait; in generateWaitcntInstBefore()
1045 AMDGPU::Waitcnt OldWait; in generateWaitcntInstBefore()
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H A DSIMachineFunctionInfo.cpp73 FrameOffsetReg = AMDGPU::SGPR5; in SIMachineFunctionInfo()
185 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass)); in addPrivateSegmentBuffer()
192 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchPtr()
199 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addQueuePtr()
207 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addKernargSegmentPtr()
214 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchID()
221 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addFlatScratchInit()
228 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addImplicitBufferPtr()
314 return AMDGPU::VGPR0; in getWorkItemIDVGPR()
317 return AMDGPU::VGPR1; in getWorkItemIDVGPR()
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H A DAMDGPUInstructionSelector.cpp110 case AMDGPU::sub0: in getSubOperand64()
112 case AMDGPU::sub1: in getSubOperand64()
150 .addImm(AMDGPU::sub0) in selectG_ADD()
152 .addImm(AMDGPU::sub1); in selectG_ADD()
222 unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP; in buildEXP()
351 unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in selectG_CONSTANT()
374 .addImm(AMDGPU::sub0) in selectG_CONSTANT()
376 .addImm(AMDGPU::sub1); in selectG_CONSTANT()
454 case AMDGPU::S_LOAD_DWORD_IMM: in getSmrdOpcode()
466 case AMDGPU::S_LOAD_DWORD_IMM_ci: in getSmrdOpcode()
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H A DGCNHazardRecognizer.cpp60 return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64; in isDivFMas()
68 return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32; in isSSetReg()
72 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
81 case AMDGPU::S_MOVRELS_B32: in isSMovRel()
82 case AMDGPU::S_MOVRELS_B64: in isSMovRel()
97 case AMDGPU::S_SENDMSG: in isSendMsgTraceDataOrGDS()
99 case AMDGPU::S_TTRACEDATA: in isSendMsgTraceDataOrGDS()
102 case AMDGPU::DS_NOP: in isSendMsgTraceDataOrGDS()
515 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
541 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in createsVALUHazard()
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H A DAMDGPUArgumentUsageInfo.cpp80 &AMDGPU::SGPR_128RegClass); in getPreloadedValue()
84 &AMDGPU::SGPR_64RegClass); in getPreloadedValue()
87 &AMDGPU::SGPR_32RegClass); in getPreloadedValue()
91 &AMDGPU::SGPR_32RegClass); in getPreloadedValue()
94 &AMDGPU::SGPR_32RegClass); in getPreloadedValue()
98 &AMDGPU::SGPR_32RegClass); in getPreloadedValue()
101 &AMDGPU::SGPR_64RegClass); in getPreloadedValue()
104 &AMDGPU::SGPR_64RegClass); in getPreloadedValue()
107 &AMDGPU::SGPR_64RegClass); in getPreloadedValue()
110 &AMDGPU::SGPR_64RegClass); in getPreloadedValue()
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H A DR600RegisterInfo.td3 let Namespace = "AMDGPU";
16 let Namespace = "AMDGPU";
22 let Namespace = "AMDGPU";
31 let Namespace = "AMDGPU";
171 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
174 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
177 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp271 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) in convertSDWAInst()
275 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); in convertSDWAInst()
411 case AMDGPU::SGPR_32RegClassID: in createSRegOperand()
412 case AMDGPU::TTMP_32RegClassID: in createSRegOperand()
643 using namespace AMDGPU; in getVgprClassId()
658 using namespace AMDGPU; in getSgprClassId()
675 using namespace AMDGPU; in getTtmpClassId()
759 using namespace AMDGPU; in decodeSpecialReg32()
791 using namespace AMDGPU; in decodeSpecialReg64()
807 using namespace AMDGPU::SDWA; in decodeSDWASrc()
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/freebsd-12.1/contrib/llvm/lib/Support/
H A DTargetParser.cpp22 using namespace AMDGPU;
29 AMDGPU::GPUKind Kind;
131 AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU) { in parseArchAMDGCN()
137 return AMDGPU::GPUKind::GK_NONE; in parseArchAMDGCN()
140 AMDGPU::GPUKind llvm::AMDGPU::parseArchR600(StringRef CPU) { in parseArchR600()
146 return AMDGPU::GPUKind::GK_NONE; in parseArchR600()
149 unsigned AMDGPU::getArchAttrAMDGCN(GPUKind AK) { in getArchAttrAMDGCN()
155 unsigned AMDGPU::getArchAttrR600(GPUKind AK) { in getArchAttrR600()
172 AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { in getIsaVersion()
176 AMDGPU::GPUKind AK = parseArchAMDGCN(GPU); in getIsaVersion()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1633 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
1638 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
1648 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
1653 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
1658 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
2455 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
3202 case AMDGPU::TBA: in subtargetHasRegister()
3205 case AMDGPU::TMA: in subtargetHasRegister()
3734 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
3769 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/InstPrinter/
H A DAMDGPUInstPrinter.cpp254 case AMDGPU::VCC: in printRegOperand()
257 case AMDGPU::SCC: in printRegOperand()
260 case AMDGPU::EXEC: in printRegOperand()
263 case AMDGPU::M0: in printRegOperand()
272 case AMDGPU::VCC_LO: in printRegOperand()
275 case AMDGPU::VCC_HI: in printRegOperand()
278 case AMDGPU::TBA_LO: in printRegOperand()
384 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
751 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1158 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printWaitFlag()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp232 case AMDGPU::OPERAND_REG_IMM_INT32: in getLitEncoding()
233 case AMDGPU::OPERAND_REG_IMM_FP32: in getLitEncoding()
235 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getLitEncoding()
238 case AMDGPU::OPERAND_REG_IMM_INT64: in getLitEncoding()
239 case AMDGPU::OPERAND_REG_IMM_FP64: in getLitEncoding()
244 case AMDGPU::OPERAND_REG_IMM_INT16: in getLitEncoding()
245 case AMDGPU::OPERAND_REG_IMM_FP16: in getLitEncoding()
332 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
342 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { in getSDWASrcEncoding()
362 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
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