Lines Matching refs:AMDGPU
65 using namespace llvm::AMDGPU;
263 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVReg()
264 isRegClass(AMDGPU::VReg_64RegClassID) || in isVReg()
265 isRegClass(AMDGPU::VReg_96RegClassID) || in isVReg()
266 isRegClass(AMDGPU::VReg_128RegClassID) || in isVReg()
267 isRegClass(AMDGPU::VReg_256RegClassID) || in isVReg()
268 isRegClass(AMDGPU::VReg_512RegClassID); in isVReg()
272 return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID); in isVReg32OrOff()
347 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); in isSCSrcB16()
355 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); in isSCSrcB32()
359 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); in isSCSrcB64()
363 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); in isSCSrcF16()
371 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); in isSCSrcF32()
375 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); in isSCSrcF64()
415 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); in isVCSrcB32()
419 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); in isVCSrcB64()
423 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); in isVCSrcB16()
431 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); in isVCSrcF32()
435 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); in isVCSrcF64()
439 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); in isVCSrcF16()
921 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
923 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { in AMDGPUAsmParser()
936 if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { in AMDGPUAsmParser()
945 return AMDGPU::hasXNACK(getSTI()); in hasXNACK()
949 return AMDGPU::hasMIMG_R128(getSTI()); in hasMIMG_R128()
953 return AMDGPU::hasPackedD16(getSTI()); in hasPackedD16()
957 return AMDGPU::isSI(getSTI()); in isSI()
961 return AMDGPU::isCI(getSTI()); in isCI()
965 return AMDGPU::isVI(getSTI()); in isVI()
969 return AMDGPU::isGFX9(getSTI()); in isGFX9()
973 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; in hasInv2PiInlineImm()
977 return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; in hasFlatOffsets()
985 return getFeatureBits()[AMDGPU::FeatureIntClamp]; in hasIntClamp()
1202 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1203 case AMDGPU::OPERAND_REG_IMM_FP32: in getOpFltSemantics()
1204 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getOpFltSemantics()
1205 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getOpFltSemantics()
1207 case AMDGPU::OPERAND_REG_IMM_INT64: in getOpFltSemantics()
1208 case AMDGPU::OPERAND_REG_IMM_FP64: in getOpFltSemantics()
1209 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in getOpFltSemantics()
1210 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in getOpFltSemantics()
1212 case AMDGPU::OPERAND_REG_IMM_INT16: in getOpFltSemantics()
1213 case AMDGPU::OPERAND_REG_IMM_FP16: in getOpFltSemantics()
1214 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in getOpFltSemantics()
1215 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in getOpFltSemantics()
1216 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in getOpFltSemantics()
1217 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in getOpFltSemantics()
1259 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1268 return AMDGPU::isInlinableLiteral16( in isInlinableImm()
1274 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1281 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1286 return AMDGPU::isInlinableLiteral16( in isInlinableImm()
1291 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1384 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
1399 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1402 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1412 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
1413 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
1414 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
1415 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
1416 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), in addLiteralImmOperand()
1423 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
1440 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
1441 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
1442 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
1443 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
1444 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
1445 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
1446 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
1447 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
1448 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
1449 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: { in addLiteralImmOperand()
1459 if (OpTy == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in addLiteralImmOperand()
1460 OpTy == AMDGPU::OPERAND_REG_INLINE_C_V2FP16) { in addLiteralImmOperand()
1478 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
1479 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
1480 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
1481 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
1483 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), in addLiteralImmOperand()
1492 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
1493 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
1494 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
1495 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
1496 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
1504 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
1505 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
1506 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
1507 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
1509 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
1518 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
1519 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: { in addLiteralImmOperand()
1521 assert(AMDGPU::isInlinableLiteral16(LiteralVal, in addLiteralImmOperand()
1552 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
1563 case 1: return AMDGPU::VGPR_32RegClassID; in getRegClass()
1564 case 2: return AMDGPU::VReg_64RegClassID; in getRegClass()
1565 case 3: return AMDGPU::VReg_96RegClassID; in getRegClass()
1566 case 4: return AMDGPU::VReg_128RegClassID; in getRegClass()
1567 case 8: return AMDGPU::VReg_256RegClassID; in getRegClass()
1568 case 16: return AMDGPU::VReg_512RegClassID; in getRegClass()
1573 case 1: return AMDGPU::TTMP_32RegClassID; in getRegClass()
1574 case 2: return AMDGPU::TTMP_64RegClassID; in getRegClass()
1575 case 4: return AMDGPU::TTMP_128RegClassID; in getRegClass()
1576 case 8: return AMDGPU::TTMP_256RegClassID; in getRegClass()
1577 case 16: return AMDGPU::TTMP_512RegClassID; in getRegClass()
1582 case 1: return AMDGPU::SGPR_32RegClassID; in getRegClass()
1583 case 2: return AMDGPU::SGPR_64RegClassID; in getRegClass()
1584 case 4: return AMDGPU::SGPR_128RegClassID; in getRegClass()
1585 case 8: return AMDGPU::SGPR_256RegClassID; in getRegClass()
1586 case 16: return AMDGPU::SGPR_512RegClassID; in getRegClass()
1594 .Case("exec", AMDGPU::EXEC) in getSpecialRegForName()
1595 .Case("vcc", AMDGPU::VCC) in getSpecialRegForName()
1596 .Case("flat_scratch", AMDGPU::FLAT_SCR) in getSpecialRegForName()
1597 .Case("xnack_mask", AMDGPU::XNACK_MASK) in getSpecialRegForName()
1598 .Case("m0", AMDGPU::M0) in getSpecialRegForName()
1599 .Case("scc", AMDGPU::SCC) in getSpecialRegForName()
1600 .Case("tba", AMDGPU::TBA) in getSpecialRegForName()
1601 .Case("tma", AMDGPU::TMA) in getSpecialRegForName()
1602 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) in getSpecialRegForName()
1603 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) in getSpecialRegForName()
1604 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) in getSpecialRegForName()
1605 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) in getSpecialRegForName()
1606 .Case("vcc_lo", AMDGPU::VCC_LO) in getSpecialRegForName()
1607 .Case("vcc_hi", AMDGPU::VCC_HI) in getSpecialRegForName()
1608 .Case("exec_lo", AMDGPU::EXEC_LO) in getSpecialRegForName()
1609 .Case("exec_hi", AMDGPU::EXEC_HI) in getSpecialRegForName()
1610 .Case("tma_lo", AMDGPU::TMA_LO) in getSpecialRegForName()
1611 .Case("tma_hi", AMDGPU::TMA_HI) in getSpecialRegForName()
1612 .Case("tba_lo", AMDGPU::TBA_LO) in getSpecialRegForName()
1613 .Case("tba_hi", AMDGPU::TBA_HI) in getSpecialRegForName()
1633 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
1634 Reg = AMDGPU::EXEC; in AddNextRegisterToList()
1638 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
1639 Reg = AMDGPU::FLAT_SCR; in AddNextRegisterToList()
1643 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { in AddNextRegisterToList()
1644 Reg = AMDGPU::XNACK_MASK; in AddNextRegisterToList()
1648 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
1649 Reg = AMDGPU::VCC; in AddNextRegisterToList()
1653 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
1654 Reg = AMDGPU::TBA; in AddNextRegisterToList()
1658 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
1659 Reg = AMDGPU::TMA; in AddNextRegisterToList()
1829 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
1864 if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { in parseRegister()
2155 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in checkTargetMatchPredicate()
2156 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in checkTargetMatchPredicate()
2159 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
2161 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
2169 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset); in checkTargetMatchPredicate()
2215 case AMDGPU::FLAT_SCR: in findImplicitSGPRReadInVOP()
2216 case AMDGPU::VCC: in findImplicitSGPRReadInVOP()
2217 case AMDGPU::M0: in findImplicitSGPRReadInVOP()
2223 return AMDGPU::NoRegister; in findImplicitSGPRReadInVOP()
2234 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) { in isInlineConstant()
2241 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant()
2245 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm()); in isInlineConstant()
2247 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm()); in isInlineConstant()
2250 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in isInlineConstant()
2251 OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16) { in isInlineConstant()
2252 return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm()); in isInlineConstant()
2254 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm()); in isInlineConstant()
2282 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { in validateConstantBusLimitations()
2287 if (SGPRUsed != AMDGPU::NoRegister) { in validateConstantBusLimitations()
2291 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateConstantBusLimitations()
2292 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
2293 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateConstantBusLimitations()
2328 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()
2336 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateEarlyClobberLimitations()
2337 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
2338 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateEarlyClobberLimitations()
2367 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
2383 int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); in validateMIMGDataSize()
2384 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
2385 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
2391 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
2400 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGDataSize()
2418 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
2436 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
2455 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
2940 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in ParseDirectiveHSACodeObjectISA()
3002 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI()); in ParseDirectiveAMDKernelCodeT()
3037 if (!AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) in ParseDirectiveAMDGPUHsaKernel()
3071 AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI()) in ParseDirectiveHSAMetadata()
3156 if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { in ParseDirective()
3164 if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) in ParseDirective()
3182 if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) in ParseDirective()
3195 for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true); in subtargetHasRegister()
3202 case AMDGPU::TBA: in subtargetHasRegister()
3203 case AMDGPU::TBA_LO: in subtargetHasRegister()
3204 case AMDGPU::TBA_HI: in subtargetHasRegister()
3205 case AMDGPU::TMA: in subtargetHasRegister()
3206 case AMDGPU::TMA_LO: in subtargetHasRegister()
3207 case AMDGPU::TMA_HI: in subtargetHasRegister()
3209 case AMDGPU::XNACK_MASK: in subtargetHasRegister()
3210 case AMDGPU::XNACK_MASK_LO: in subtargetHasRegister()
3211 case AMDGPU::XNACK_MASK_HI: in subtargetHasRegister()
3223 case AMDGPU::FLAT_SCR: in subtargetHasRegister()
3224 case AMDGPU::FLAT_SCR_LO: in subtargetHasRegister()
3225 case AMDGPU::FLAT_SCR_HI: in subtargetHasRegister()
3234 for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true); in subtargetHasRegister()
3593 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSOffset01()
3619 (Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_si || in cvtDSImpl()
3620 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle : in cvtDSImpl()
3628 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSImpl()
3653 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister)); in cvtExp()
3676 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
3677 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
3681 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
3698 const AMDGPU::IsaVersion ISA, in encodeCnt()
3734 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
3769 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
3794 using namespace llvm::AMDGPU::Hwreg; in parseHwregConstruct()
3858 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()
3909 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgConstruct()
4146 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgOp()
4287 using namespace llvm::AMDGPU::Swizzle; in encodeBitmaskPerm()
4319 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleQuadPerm()
4335 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBroadcast()
4361 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleReverse()
4381 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleSwap()
4401 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBitmaskPerm()
4463 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleMacro()
4606 int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode()); in cvtMubufImpl()
4920 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3OpSel()
4921 AMDGPU::OpName::src1, in cvtVOP3OpSel()
4922 AMDGPU::OpName::src2 }; in cvtVOP3OpSel()
4924 SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1; in cvtVOP3OpSel()
4928 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3OpSel()
4932 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in cvtVOP3OpSel()
4940 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS in isRegOrImmWithInputMods()
4975 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) { in cvtVOP3Interp()
4979 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3Interp()
4983 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3Interp()
4998 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) { in cvtVOP3()
5024 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3()
5028 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3()
5036 if (Opc == AMDGPU::V_MAC_F32_e64_si || in cvtVOP3()
5037 Opc == AMDGPU::V_MAC_F32_e64_vi || in cvtVOP3()
5038 Opc == AMDGPU::V_MAC_F16_e64_vi || in cvtVOP3()
5039 Opc == AMDGPU::V_FMAC_F32_e64_vi) { in cvtVOP3()
5041 std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers)); in cvtVOP3()
5063 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) { in cvtVOP3P()
5073 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in cvtVOP3P()
5080 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); in cvtVOP3P()
5087 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3P()
5088 AMDGPU::OpName::src1, in cvtVOP3P()
5089 AMDGPU::OpName::src2 }; in cvtVOP3P()
5090 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVOP3P()
5091 AMDGPU::OpName::src1_modifiers, in cvtVOP3P()
5092 AMDGPU::OpName::src2_modifiers }; in cvtVOP3P()
5094 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3P()
5106 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi); in cvtVOP3P()
5112 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVOP3P()
5130 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVOP3P()
5141 using namespace AMDGPU::DPP; in isDPPCtrl()
5176 using namespace AMDGPU::DPP; in parseDPPCtrl()
5306 if (Op.isReg() && Op.Reg.RegNo == AMDGPU::VCC) { in cvtDPP()
5334 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
5367 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
5412 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()
5425 if (skipVcc && !skippedVcc && Op.isReg() && Op.Reg.RegNo == AMDGPU::VCC) { in cvtSDWA()
5451 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 && in cvtSDWA()
5452 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) { in cvtSDWA()
5457 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
5467 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
5489 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in cvtSDWA()
5490 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in cvtSDWA()
5493 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); in cvtSDWA()