Lines Matching refs:AMDGPU
28 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(), in getAllSGPR128()
34 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), in getAllSGPRs()
67 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitFlatScratchInit()
68 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitFlatScratchInit()
74 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO) in emitFlatScratchInit()
77 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI) in emitFlatScratchInit()
85 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO) in emitFlatScratchInit()
90 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo) in emitFlatScratchInit()
95 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI) in emitFlatScratchInit()
110 if (ScratchRsrcReg == AMDGPU::NoRegister || in getReservedPrivateSegmentBufferReg()
112 return AMDGPU::NoRegister; in getReservedPrivateSegmentBufferReg()
161 if (ScratchWaveOffsetReg == AMDGPU::NoRegister || in getReservedPrivateSegmentWaveByteOffsetReg()
163 assert(MFI->getStackPtrOffsetReg() == AMDGPU::SP_REG); in getReservedPrivateSegmentWaveByteOffsetReg()
164 return std::make_pair(AMDGPU::NoRegister, AMDGPU::NoRegister); in getReservedPrivateSegmentWaveByteOffsetReg()
255 if (SPReg != AMDGPU::SP_REG) { in emitEntryFunctionPrologue()
263 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg) in emitEntryFunctionPrologue()
266 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::S_ADD_U32), SPReg) in emitEntryFunctionPrologue()
282 if (ScratchWaveOffsetReg == AMDGPU::NoRegister) { in emitEntryFunctionPrologue()
283 assert(ScratchRsrcReg == AMDGPU::NoRegister); in emitEntryFunctionPrologue()
291 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister; in emitEntryFunctionPrologue()
298 bool ResourceRegUsed = ScratchRsrcReg != AMDGPU::NoRegister && in emitEntryFunctionPrologue()
304 assert(PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister && in emitEntryFunctionPrologue()
310 if (ResourceRegUsed && PreloadedPrivateBufferReg != AMDGPU::NoRegister) { in emitEntryFunctionPrologue()
335 PreloadedPrivateBufferReg != AMDGPU::NoRegister && in emitEntryFunctionPrologue()
345 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg) in emitEntryFunctionPrologue()
351 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg) in emitEntryFunctionPrologue()
357 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg) in emitEntryFunctionPrologue()
380 unsigned RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
381 unsigned RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
382 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
384 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); in emitEntryFunctionScratchSetup()
391 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64); in emitEntryFunctionScratchSetup()
394 auto GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in in emitEntryFunctionScratchSetup()
401 GitPtrLo = AMDGPU::SGPR8; in emitEntryFunctionScratchSetup()
419 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM); in emitEntryFunctionScratchSetup()
435 || (PreloadedPrivateBufferReg == AMDGPU::NoRegister)) { in emitEntryFunctionScratchSetup()
437 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); in emitEntryFunctionScratchSetup()
439 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchSetup()
440 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchSetup()
446 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchSetup()
448 if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { in emitEntryFunctionScratchSetup()
449 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64); in emitEntryFunctionScratchSetup()
455 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM); in emitEntryFunctionScratchSetup()
474 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchSetup()
475 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchSetup()
523 for (unsigned Reg : AMDGPU::SReg_32_XM0RegClass) { in findScratchNonCalleeSaveRegister()
528 return AMDGPU::NoRegister; in findScratchNonCalleeSaveRegister()
564 assert(ScratchSPReg != AMDGPU::NoRegister); in emitPrologue()
568 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg) in emitPrologue()
572 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg) in emitPrologue()
582 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg) in emitPrologue()
588 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg) in emitPrologue()
599 Reg.FI.getValue(), &AMDGPU::VGPR_32RegClass, in emitPrologue()
619 Reg.FI.getValue(), &AMDGPU::VGPR_32RegClass, in emitEpilogue()
624 if (StackPtrReg == AMDGPU::NoRegister) in emitEpilogue()
639 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg) in emitEpilogue()
695 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex(); in processFunctionBeforeFrameFinalized()
731 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false); in processFunctionBeforeFrameFinalized()
769 unsigned Op = IsDestroy ? AMDGPU::S_SUB_U32 : AMDGPU::S_ADD_U32; in eliminateCallFramePseudoInstr()
800 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitDebuggerPrologue()
801 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR) in emitDebuggerPrologue()
807 WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI); in emitDebuggerPrologue()
817 WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI); in emitDebuggerPrologue()