122   auto DPP32 = AMDGPU::getDPPOp32(Op);  in getDPPOp()
126   auto E32 = AMDGPU::getVOPe32(Op);  in getDPPOp()
127   return E32 != -1 ? AMDGPU::getDPPOp32(E32) : -1;  in getDPPOp()
141   case AMDGPU::IMPLICIT_DEF:  in getOldOpndValue()
143   case AMDGPU::COPY:  in getOldOpndValue()
144   case AMDGPU::V_MOV_B32_e32: {  in getOldOpndValue()
158   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);  in createDPPInst()
159   assert(TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg() ==  in createDPPInst()
160          TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)->getReg());  in createDPPInst()
173     auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);  in createDPPInst()
178     const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);  in createDPPInst()
181       assert(isOfRegClass(OldOpndVGPR, AMDGPU::VGPR_32RegClass, *MRI));  in createDPPInst()
187                                           AMDGPU::OpName::src0_modifiers)) {  in createDPPInst()
188       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
189                                           AMDGPU::OpName::src0_modifiers));  in createDPPInst()
194     auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);  in createDPPInst()
205                                           AMDGPU::OpName::src1_modifiers)) {  in createDPPInst()
206       assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,  in createDPPInst()
207                                           AMDGPU::OpName::src1_modifiers));  in createDPPInst()
212     if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {  in createDPPInst()
222     if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {  in createDPPInst()
231     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));  in createDPPInst()
232     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));  in createDPPInst()
233     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));  in createDPPInst()
252   case AMDGPU::V_MAX_U32_e32:  in foldOldOpnd()
256   case AMDGPU::V_MAX_I32_e32:  in foldOldOpnd()
260   case AMDGPU::V_MIN_I32_e32:  in foldOldOpnd()
265   case AMDGPU::V_MUL_I32_I24_e32:  in foldOldOpnd()
266   case AMDGPU::V_MUL_U32_U24_e32:  in foldOldOpnd()
268       auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);  in foldOldOpnd()
318   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);  in combineDPPMov()
319   auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);  in combineDPPMov()
325   auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);  in combineDPPMov()
332       OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef, ignore old opnd  in combineDPPMov()
340         OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef  in combineDPPMov()
357       MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));  in combineDPPMov()
359                              TII->get(AMDGPU::IMPLICIT_DEF), OldOpndVGPR.Reg);  in combineDPPMov()
366        TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg())) {  in combineDPPMov()
378       if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||  in combineDPPMov()
379           !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||  in combineDPPMov()
380           !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||  in combineDPPMov()
381           !hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {  in combineDPPMov()
391     if (&Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) {  in combineDPPMov()
398                &Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {  in combineDPPMov()
439       if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {  in runOnMachineFunction()