Lines Matching refs:AMDGPU
65 PSInputAddr = AMDGPU::getInitialPSInputAddr(F); in SIMachineFunctionInfo()
71 ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3; in SIMachineFunctionInfo()
72 ScratchWaveOffsetReg = AMDGPU::SGPR4; in SIMachineFunctionInfo()
73 FrameOffsetReg = AMDGPU::SGPR5; in SIMachineFunctionInfo()
74 StackPtrOffsetReg = AMDGPU::SGPR32; in SIMachineFunctionInfo()
134 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
185 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass)); in addPrivateSegmentBuffer()
192 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchPtr()
199 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addQueuePtr()
207 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addKernargSegmentPtr()
214 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchID()
221 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addFlatScratchInit()
228 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addImplicitBufferPtr()
272 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); in allocateSGPRSpillToVGPR()
273 if (LaneVGPR == AMDGPU::NoRegister) { in allocateSGPRSpillToVGPR()
314 return AMDGPU::VGPR0; in getWorkItemIDVGPR()
317 return AMDGPU::VGPR1; in getWorkItemIDVGPR()
320 return AMDGPU::VGPR2; in getWorkItemIDVGPR()
327 return AMDGPU::SGPR0 + NumUserSGPRs; in getNextUserSGPR()
331 return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; in getNextSystemSGPR()