60   return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64;  in isDivFMas()
64   return Opcode == AMDGPU::S_GETREG_B32;  in isSGetReg()
68   return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32;  in isSSetReg()
72   return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32;  in isRWLane()
76   return Opcode == AMDGPU::S_RFE_B64;  in isRFE()
81   case AMDGPU::S_MOVRELS_B32:  in isSMovRel()
82   case AMDGPU::S_MOVRELS_B64:  in isSMovRel()
83   case AMDGPU::S_MOVRELD_B32:  in isSMovRel()
84   case AMDGPU::S_MOVRELD_B64:  in isSMovRel()
97   case AMDGPU::S_SENDMSG:  in isSendMsgTraceDataOrGDS()
98   case AMDGPU::S_SENDMSGHALT:  in isSendMsgTraceDataOrGDS()
99   case AMDGPU::S_TTRACEDATA:  in isSendMsgTraceDataOrGDS()
102   case AMDGPU::DS_NOP:  in isSendMsgTraceDataOrGDS()
103   case AMDGPU::DS_PERMUTE_B32:  in isSendMsgTraceDataOrGDS()
104   case AMDGPU::DS_BPERMUTE_B32:  in isSendMsgTraceDataOrGDS()
108       int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in isSendMsgTraceDataOrGDS()
109                                            AMDGPU::OpName::gds);  in isSendMsgTraceDataOrGDS()
119                                                      AMDGPU::OpName::simm16);  in getHWReg()
120   return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;  in getHWReg()
235   if (CurrCycleInstr->getOpcode() == AMDGPU::IMPLICIT_DEF)  in AdvanceCycle()
278       if (Opcode == AMDGPU::INLINEASM)  in getWaitStatesSince()
464       DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn));  in checkDPPHazards()
476   int WaitStatesNeeded = getWaitStatesSinceDef(AMDGPU::VCC, IsHazardDefFn);  in checkDivFMasHazards()
515   int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);  in createsVALUHazard()
528         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);  in createsVALUHazard()
531     if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&  in createsVALUHazard()
541     int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);  in createsVALUHazard()
543            AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);  in createsVALUHazard()
548     int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);  in createsVALUHazard()
549     if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)  in createsVALUHazard()
628       TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);  in checkRWLaneHazards()
652     return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;  in checkRFEHazards()
675       return MI->getOpcode() == AMDGPU::S_MOV_FED_B32;  in checkAnyInstHazards()
691   return SMovRelWaitStates - getWaitStatesSinceDef(AMDGPU::M0, IsHazardFn);  in checkReadM0Hazards()