133       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit16Encoding()
169       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit32Encoding()
205       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit64Encoding()
232   case AMDGPU::OPERAND_REG_IMM_INT32:  in getLitEncoding()
233   case AMDGPU::OPERAND_REG_IMM_FP32:  in getLitEncoding()
234   case AMDGPU::OPERAND_REG_INLINE_C_INT32:  in getLitEncoding()
235   case AMDGPU::OPERAND_REG_INLINE_C_FP32:  in getLitEncoding()
238   case AMDGPU::OPERAND_REG_IMM_INT64:  in getLitEncoding()
239   case AMDGPU::OPERAND_REG_IMM_FP64:  in getLitEncoding()
240   case AMDGPU::OPERAND_REG_INLINE_C_INT64:  in getLitEncoding()
241   case AMDGPU::OPERAND_REG_INLINE_C_FP64:  in getLitEncoding()
244   case AMDGPU::OPERAND_REG_IMM_INT16:  in getLitEncoding()
245   case AMDGPU::OPERAND_REG_IMM_FP16:  in getLitEncoding()
246   case AMDGPU::OPERAND_REG_INLINE_C_INT16:  in getLitEncoding()
247   case AMDGPU::OPERAND_REG_INLINE_C_FP16:  in getLitEncoding()
252   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:  in getLitEncoding()
253   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {  in getLitEncoding()
284     if (!AMDGPU::isSISrcOperand(Desc, i))  in encodeInstruction()
320     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;  in getSOPPBrEncoding()
332   using namespace AMDGPU::SDWA;  in getSDWASrcEncoding()
342     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {  in getSDWASrcEncoding()
362   using namespace AMDGPU::SDWA;  in getSDWAVopcDstEncoding()
369   if (Reg != AMDGPU::VCC) {  in getSDWAVopcDstEncoding()
430   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {  in getMachineOpValue()