75   return MI.getOpcode() == AMDGPU::S_OR_B64 &&  in isEndCF()
76          MI.modifiesRegister(AMDGPU::EXEC, TRI);  in isEndCF()
80   return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;  in isFullExecCopy()
85   auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);  in getOrNonExecReg()
86   if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)  in getOrNonExecReg()
88   Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);  in getOrNonExecReg()
89   if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)  in getOrNonExecReg()
91   return AMDGPU::NoRegister;  in getOrNonExecReg()
98   if (SavedExec == AMDGPU::NoRegister)  in getOrExecSource()
128   const unsigned AndOpc = AMDGPU::S_AND_B64;  in optimizeVcndVcmpPair()
129   const unsigned Andn2Opc = AMDGPU::S_ANDN2_B64;  in optimizeVcndVcmpPair()
130   const unsigned CondReg = AMDGPU::VCC;  in optimizeVcndVcmpPair()
131   const unsigned ExecReg = AMDGPU::EXEC;  in optimizeVcndVcmpPair()
135                            return Opc == AMDGPU::S_CBRANCH_VCCZ ||  in optimizeVcndVcmpPair()
136                                   Opc == AMDGPU::S_CBRANCH_VCCNZ; });  in optimizeVcndVcmpPair()
138     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
140   auto *And = TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister,  in optimizeVcndVcmpPair()
144     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
154     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
158   if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||  in optimizeVcndVcmpPair()
159                 Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||  in optimizeVcndVcmpPair()
161     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
163   MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);  in optimizeVcndVcmpPair()
164   MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);  in optimizeVcndVcmpPair()
168     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
172   if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)  in optimizeVcndVcmpPair()
173     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
175   Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);  in optimizeVcndVcmpPair()
176   Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);  in optimizeVcndVcmpPair()
177   MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);  in optimizeVcndVcmpPair()
180     return AMDGPU::NoRegister;  in optimizeVcndVcmpPair()
231   DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});  in runOnMachineFunction()
238       RecalcRegs.insert(AMDGPU::VCC_LO);  in runOnMachineFunction()
239       RecalcRegs.insert(AMDGPU::VCC_HI);  in runOnMachineFunction()
240       RecalcRegs.insert(AMDGPU::SCC);  in runOnMachineFunction()
252       if (Term.getOpcode() != AMDGPU::S_ENDPGM ||  in runOnMachineFunction()
262           if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)  in runOnMachineFunction()
318       if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))  in runOnMachineFunction()
366       MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);  in runOnMachineFunction()