67   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);  in insertNamedMCOperand()
180   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding])  in getInstruction()
204       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {  in getInstruction()
213       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {  in getInstruction()
246   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||  in getInstruction()
247               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||  in getInstruction()
248               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||  in getInstruction()
249               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi)) {  in getInstruction()
252                          AMDGPU::OpName::src2_modifiers);  in getInstruction()
270   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {  in convertSDWAInst()
271     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)  in convertSDWAInst()
273       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);  in convertSDWAInst()
274   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {  in convertSDWAInst()
275     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);  in convertSDWAInst()
278       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),  in convertSDWAInst()
279                            AMDGPU::OpName::sdst);  in convertSDWAInst()
282       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);  in convertSDWAInst()
293   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
294                                            AMDGPU::OpName::vdst);  in convertMIMGInst()
296   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
297                                             AMDGPU::OpName::vdata);  in convertMIMGInst()
299   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
300                                             AMDGPU::OpName::dmask);  in convertMIMGInst()
302   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
303                                             AMDGPU::OpName::tfe);  in convertMIMGInst()
304   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in convertMIMGInst()
305                                             AMDGPU::OpName::d16);  in convertMIMGInst()
323   if (D16 && AMDGPU::hasPackedD16(STI)) {  in convertMIMGInst()
334     if (D16 && AMDGPU::hasPackedD16(STI))  in convertMIMGInst()
335       NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), 2);  in convertMIMGInst()
339     NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), DstSize);  in convertMIMGInst()
348   unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);  in convertMIMGInst()
352   auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,  in convertMIMGInst()
354   if (NewVdata == AMDGPU::NoRegister) {  in convertMIMGInst()
391   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));  in createRegOperand()
411   case AMDGPU::SGPR_32RegClassID:  in createSRegOperand()
412   case AMDGPU::TTMP_32RegClassID:  in createSRegOperand()
414   case AMDGPU::SGPR_64RegClassID:  in createSRegOperand()
415   case AMDGPU::TTMP_64RegClassID:  in createSRegOperand()
418   case AMDGPU::SGPR_128RegClassID:  in createSRegOperand()
419   case AMDGPU::TTMP_128RegClassID:  in createSRegOperand()
422   case AMDGPU::SGPR_256RegClassID:  in createSRegOperand()
423   case AMDGPU::TTMP_256RegClassID:  in createSRegOperand()
426   case AMDGPU::SGPR_512RegClassID:  in createSRegOperand()
427   case AMDGPU::TTMP_512RegClassID:  in createSRegOperand()
470   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);  in decodeOperand_VGPR_32()
474   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);  in decodeOperand_VReg_64()
478   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);  in decodeOperand_VReg_96()
482   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);  in decodeOperand_VReg_128()
540   using namespace AMDGPU::EncValues;  in decodeIntImmed()
625   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN  in decodeFPImmed()
626       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);  in decodeFPImmed()
643   using namespace AMDGPU;  in getVgprClassId()
658   using namespace AMDGPU;  in getSgprClassId()
675   using namespace AMDGPU;  in getTtmpClassId()
692   using namespace AMDGPU::EncValues;  in getTTmpIdx()
701   using namespace AMDGPU::EncValues;  in decodeSrcOp()
740   using namespace AMDGPU::EncValues;  in decodeDstOp()
759   using namespace AMDGPU;  in decodeSpecialReg32()
791   using namespace AMDGPU;  in decodeSpecialReg64()
807   using namespace AMDGPU::SDWA;  in decodeSDWASrc()
808   using namespace AMDGPU::EncValues;  in decodeSDWASrc()
810   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {  in decodeSDWASrc()
838   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {  in decodeSDWASrc()
853   using namespace AMDGPU::SDWA;  in decodeSDWAVopcDst()
855   assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] &&  in decodeSDWAVopcDst()
863     } else if (Val > AMDGPU::EncValues::SGPR_MAX) {  in decodeSDWAVopcDst()
869     return createRegOperand(AMDGPU::VCC);  in decodeSDWAVopcDst()
874   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];  in isVI()
878   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];  in isGFX9()