74   int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in foldImmediates()
187   int SOPKOpc = AMDGPU::getSOPKOp(MI.getOpcode());  in shrinkScalarCompare()
193   if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {  in shrinkScalarCompare()
197         SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ?  in shrinkScalarCompare()
198           AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32;  in shrinkScalarCompare()
232       !AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
236     if (Opc == AMDGPU::S_AND_B32) {  in shrinkScalarLogicOp()
239         Opc = AMDGPU::S_BITSET0_B32;  in shrinkScalarLogicOp()
240       } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
242         Opc = AMDGPU::S_ANDN2_B32;  in shrinkScalarLogicOp()
244     } else if (Opc == AMDGPU::S_OR_B32) {  in shrinkScalarLogicOp()
247         Opc = AMDGPU::S_BITSET1_B32;  in shrinkScalarLogicOp()
248       } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
250         Opc = AMDGPU::S_ORN2_B32;  in shrinkScalarLogicOp()
252     } else if (Opc == AMDGPU::S_XOR_B32) {  in shrinkScalarLogicOp()
253       if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
255         Opc = AMDGPU::S_XNOR_B32;  in shrinkScalarLogicOp()
261     if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) &&  in shrinkScalarLogicOp()
277         if (Opc == AMDGPU::S_BITSET0_B32 ||  in shrinkScalarLogicOp()
278             Opc == AMDGPU::S_BITSET1_B32) {  in shrinkScalarLogicOp()
362   assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||  in matchSwap()
363          MovT.getOpcode() == AMDGPU::COPY);  in matchSwap()
385     if ((MovY.getOpcode() != AMDGPU::V_MOV_B32_e32 &&  in matchSwap()
386          MovY.getOpcode() != AMDGPU::COPY) ||  in matchSwap()
414           (I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&  in matchSwap()
415            I->getOpcode() != AMDGPU::COPY) ||  in matchSwap()
434                 TII->get(AMDGPU::V_SWAP_B32))  in matchSwap()
473       if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {  in runOnMachineFunction()
487             MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));  in runOnMachineFunction()
494       if (ST.hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||  in runOnMachineFunction()
495                            MI.getOpcode() == AMDGPU::COPY)) {  in runOnMachineFunction()
509       if (MI.getOpcode() == AMDGPU::S_NOP &&  in runOnMachineFunction()
511           (*Next).getOpcode() == AMDGPU::S_NOP) {  in runOnMachineFunction()
534       if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||  in runOnMachineFunction()
535           MI.getOpcode() == AMDGPU::S_MUL_I32) {  in runOnMachineFunction()
557             unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?  in runOnMachineFunction()
558               AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;  in runOnMachineFunction()
573       if (MI.getOpcode() == AMDGPU::S_MOV_B32) {  in runOnMachineFunction()
581             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));  in runOnMachineFunction()
583             MI.setDesc(TII->get(AMDGPU::S_BREV_B32));  in runOnMachineFunction()
592       if (MI.getOpcode() == AMDGPU::S_AND_B32 ||  in runOnMachineFunction()
593           MI.getOpcode() == AMDGPU::S_OR_B32 ||  in runOnMachineFunction()
594           MI.getOpcode() == AMDGPU::S_XOR_B32) {  in runOnMachineFunction()
615       int Op32 = AMDGPU::getVOPe32(MI.getOpcode());  in runOnMachineFunction()
628           MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);  in runOnMachineFunction()
631         if (DstReg != AMDGPU::VCC)  in runOnMachineFunction()
635       if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {  in runOnMachineFunction()
639             TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in runOnMachineFunction()
644           MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC);  in runOnMachineFunction()
647         if (SReg != AMDGPU::VCC)  in runOnMachineFunction()
653                                                         AMDGPU::OpName::sdst);  in runOnMachineFunction()
657                                                         AMDGPU::OpName::src2);  in runOnMachineFunction()
660         if (SDst->getReg() != AMDGPU::VCC) {  in runOnMachineFunction()
662             MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC);  in runOnMachineFunction()
668         if (Src2 && Src2->getReg() != AMDGPU::VCC) {  in runOnMachineFunction()
670             MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC);  in runOnMachineFunction()