134       if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||  in shouldSkip()
135           I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)  in shouldSkip()
163   BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))  in skipIfDead()
169   BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))  in skipIfDead()
171     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
172     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
173     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
174     .addReg(AMDGPU::VGPR0, RegState::Undef)  in skipIfDead()
180   BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));  in skipIfDead()
190   case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR: {  in kill()
198       Opcode = AMDGPU::V_CMPX_EQ_F32_e64;  in kill()
202       Opcode = AMDGPU::V_CMPX_LT_F32_e64;  in kill()
206       Opcode = AMDGPU::V_CMPX_LE_F32_e64;  in kill()
210       Opcode = AMDGPU::V_CMPX_GT_F32_e64;  in kill()
214       Opcode = AMDGPU::V_CMPX_GE_F32_e64;  in kill()
218       Opcode = AMDGPU::V_CMPX_LG_F32_e64;  in kill()
221       Opcode = AMDGPU::V_CMPX_O_F32_e64;  in kill()
224       Opcode = AMDGPU::V_CMPX_U_F32_e64;  in kill()
227       Opcode = AMDGPU::V_CMPX_NLG_F32_e64;  in kill()
230       Opcode = AMDGPU::V_CMPX_NGE_F32_e64;  in kill()
233       Opcode = AMDGPU::V_CMPX_NGT_F32_e64;  in kill()
236       Opcode = AMDGPU::V_CMPX_NLE_F32_e64;  in kill()
239       Opcode = AMDGPU::V_CMPX_NLT_F32_e64;  in kill()
242       Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;  in kill()
252       Opcode = AMDGPU::getVOPe32(Opcode);  in kill()
258           .addReg(AMDGPU::VCC, RegState::Define)  in kill()
267   case AMDGPU::SI_KILL_I1_TERMINATOR: {  in kill()
278         BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)  in kill()
283     unsigned Opcode = KillVal ? AMDGPU::S_ANDN2_B64 : AMDGPU::S_AND_B64;  in kill()
284     BuildMI(MBB, &MI, DL, TII->get(Opcode), AMDGPU::EXEC)  in kill()
285         .addReg(AMDGPU::EXEC)  in kill()
319   BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))  in skipMaskBranch()
334   const unsigned CondReg = AMDGPU::VCC;  in optimizeVccBranch()
335   const unsigned ExecReg = AMDGPU::EXEC;  in optimizeVccBranch()
336   const unsigned And = AMDGPU::S_AND_B64;  in optimizeVccBranch()
368   unsigned SReg = AMDGPU::NoRegister;  in optimizeVccBranch()
393   if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&  in optimizeVccBranch()
397   bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;  in optimizeVccBranch()
403     MI.setDesc(TII->get(AMDGPU::S_BRANCH));  in optimizeVccBranch()
405     MI.setDesc(TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ  in optimizeVccBranch()
406                                : AMDGPU::S_CBRANCH_EXECNZ));  in optimizeVccBranch()
455       case AMDGPU::SI_MASK_BRANCH:  in runOnMachineFunction()
460       case AMDGPU::S_BRANCH:  in runOnMachineFunction()
473       case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:  in runOnMachineFunction()
474       case AMDGPU::SI_KILL_I1_TERMINATOR:  in runOnMachineFunction()
491       case AMDGPU::SI_RETURN_TO_EPILOG:  in runOnMachineFunction()
506           BuildMI(*BI, I, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))  in runOnMachineFunction()
512       case AMDGPU::S_CBRANCH_VCCZ:  in runOnMachineFunction()
513       case AMDGPU::S_CBRANCH_VCCNZ:  in runOnMachineFunction()