Lines Matching refs:AMDGPU
102 BUFFER_LOAD_OFFEN = AMDGPU::BUFFER_LOAD_DWORD_OFFEN,
103 BUFFER_LOAD_OFFSET = AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
104 BUFFER_STORE_OFFEN = AMDGPU::BUFFER_STORE_DWORD_OFFEN,
105 BUFFER_STORE_OFFSET = AMDGPU::BUFFER_STORE_DWORD_OFFSET,
106 BUFFER_LOAD_OFFEN_exact = AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact,
107 BUFFER_LOAD_OFFSET_exact = AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact,
108 BUFFER_STORE_OFFEN_exact = AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact,
109 BUFFER_STORE_OFFSET_exact = AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact,
391 return AMDGPU::getMUBUFDwords(Opc); in getOpcodeWidth()
397 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
399 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getOpcodeWidth()
401 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getOpcodeWidth()
408 const int baseOpcode = AMDGPU::getMUBUFBaseOpcode(Opc); in getInstClass()
418 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getInstClass()
420 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getInstClass()
422 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getInstClass()
424 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getInstClass()
426 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: in getInstClass()
428 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: in getInstClass()
430 case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: in getInstClass()
432 case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: in getInstClass()
440 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstClass()
441 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstClass()
442 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstClass()
444 case AMDGPU::DS_READ_B32: in getInstClass()
445 case AMDGPU::DS_READ_B64: in getInstClass()
446 case AMDGPU::DS_READ_B32_gfx9: in getInstClass()
447 case AMDGPU::DS_READ_B64_gfx9: in getInstClass()
449 case AMDGPU::DS_WRITE_B32: in getInstClass()
450 case AMDGPU::DS_WRITE_B64: in getInstClass()
451 case AMDGPU::DS_WRITE_B32_gfx9: in getInstClass()
452 case AMDGPU::DS_WRITE_B64_gfx9: in getInstClass()
461 if (AMDGPU::getMUBUFHasVAddr(Opc)) { in getRegs()
465 if (AMDGPU::getMUBUFHasSrsrc(Opc)) { in getRegs()
469 if (AMDGPU::getMUBUFHasSoffset(Opc)) { in getRegs()
479 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getRegs()
480 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getRegs()
481 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getRegs()
483 case AMDGPU::DS_READ_B32: in getRegs()
484 case AMDGPU::DS_READ_B64: in getRegs()
485 case AMDGPU::DS_READ_B32_gfx9: in getRegs()
486 case AMDGPU::DS_READ_B64_gfx9: in getRegs()
487 case AMDGPU::DS_WRITE_B32: in getRegs()
488 case AMDGPU::DS_WRITE_B64: in getRegs()
489 case AMDGPU::DS_WRITE_B32_gfx9: in getRegs()
490 case AMDGPU::DS_WRITE_B64_gfx9: in getRegs()
515 AddrOpName[NumAddresses++] = AMDGPU::OpName::addr; in findMatchingInst()
519 AddrOpName[NumAddresses++] = AMDGPU::OpName::sbase; in findMatchingInst()
523 AddrOpName[NumAddresses++] = AMDGPU::OpName::srsrc; in findMatchingInst()
527 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in findMatchingInst()
531 AddrOpName[NumAddresses++] = AMDGPU::OpName::vaddr; in findMatchingInst()
535 AddrIdx[i] = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AddrOpName[i]); in findMatchingInst()
626 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::offset); in findMatchingInst()
637 CI.GLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::glc)->getImm(); in findMatchingInst()
638 CI.GLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::glc)->getImm(); in findMatchingInst()
640 CI.SLC0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::slc)->getImm(); in findMatchingInst()
641 CI.SLC1 = TII->getNamedOperand(*MBBI, AMDGPU::OpName::slc)->getImm(); in findMatchingInst()
668 return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in read2Opcode()
669 return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9; in read2Opcode()
674 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in read2ST64Opcode()
676 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9 in read2ST64Opcode()
677 : AMDGPU::DS_READ2ST64_B64_gfx9; in read2ST64Opcode()
686 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
688 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
689 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdst); in mergeRead2Pair()
696 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
697 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
711 (CI.EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass; in mergeRead2Pair()
720 unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in mergeRead2Pair()
721 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
724 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair()
765 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in write2Opcode()
766 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9 in write2Opcode()
767 : AMDGPU::DS_WRITE2_B64_gfx9; in write2Opcode()
772 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 in write2ST64Opcode()
773 : AMDGPU::DS_WRITE2ST64_B64; in write2ST64Opcode()
775 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9 in write2ST64Opcode()
776 : AMDGPU::DS_WRITE2ST64_B64_gfx9; in write2ST64Opcode()
786 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
788 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
790 TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::data0); in mergeWrite2Pair()
813 unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass); in mergeWrite2Pair()
814 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
817 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair()
858 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
869 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
870 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
905 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
907 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
908 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
921 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
922 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
944 return AMDGPU::getMUBUFOpcode(CI.InstClass, Width); in getNewOpcode()
952 return AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM; in getNewOpcode()
954 return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM; in getNewOpcode()
970 return std::make_pair(AMDGPU::sub1, AMDGPU::sub0); in getSubRegIdxs()
972 return std::make_pair(AMDGPU::sub2, AMDGPU::sub0_sub1); in getSubRegIdxs()
974 return std::make_pair(AMDGPU::sub3, AMDGPU::sub0_sub1_sub2); in getSubRegIdxs()
981 return std::make_pair(AMDGPU::sub1_sub2, AMDGPU::sub0); in getSubRegIdxs()
983 return std::make_pair(AMDGPU::sub2_sub3, AMDGPU::sub0_sub1); in getSubRegIdxs()
990 return std::make_pair(AMDGPU::sub1_sub2_sub3, AMDGPU::sub0); in getSubRegIdxs()
1002 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1); in getSubRegIdxs()
1004 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1_sub2); in getSubRegIdxs()
1006 return std::make_pair(AMDGPU::sub0, AMDGPU::sub1_sub2_sub3); in getSubRegIdxs()
1013 return std::make_pair(AMDGPU::sub0_sub1, AMDGPU::sub2); in getSubRegIdxs()
1015 return std::make_pair(AMDGPU::sub0_sub1, AMDGPU::sub2_sub3); in getSubRegIdxs()
1022 return std::make_pair(AMDGPU::sub0_sub1_sub2, AMDGPU::sub3); in getSubRegIdxs()
1035 return &AMDGPU::SReg_64_XEXECRegClass; in getTargetRegisterClass()
1037 return &AMDGPU::SReg_128RegClass; in getTargetRegisterClass()
1039 return &AMDGPU::SReg_256RegClass; in getTargetRegisterClass()
1041 return &AMDGPU::SReg_512RegClass; in getTargetRegisterClass()
1048 return &AMDGPU::VReg_64RegClass; in getTargetRegisterClass()
1050 return &AMDGPU::VReg_96RegClass; in getTargetRegisterClass()
1052 return &AMDGPU::VReg_128RegClass; in getTargetRegisterClass()
1072 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1073 const auto *Src1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1075 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1087 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1089 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1090 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1111 unsigned Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in createRegOrImm()
1114 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1140 unsigned CarryReg = MRI->createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in computeBase()
1142 MRI->createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); in computeBase()
1144 unsigned DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1145 unsigned DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1147 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_I32_e64), DestSub0) in computeBase()
1155 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1163 unsigned FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass); in computeBase()
1167 .addImm(AMDGPU::sub0) in computeBase()
1169 .addImm(AMDGPU::sub1); in computeBase()
1180 TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase); in updateBaseAndOffset()
1181 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
1193 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 || in extractConstOffset()
1216 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE in processBaseWithConstOffset()
1228 if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_I32_e64 || in processBaseWithConstOffset()
1229 !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64) in processBaseWithConstOffset()
1232 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1233 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1244 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1245 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1269 if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0 || in promoteConstantOffsetToImm()
1270 TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL) in promoteConstantOffsetToImm()
1282 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
1288 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
1347 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
1351 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
1446 (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8 in optimizeBlock()
1457 (Opc == AMDGPU::DS_WRITE_B64 || Opc == AMDGPU::DS_WRITE_B64_gfx9) ? 8 in optimizeBlock()
1467 CI.EltSize = AMDGPU::getSMRDEncodedOffset(*STM, 4); in optimizeBlock()