89   unsigned DstReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);  in getSubOperand64()
94     BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)  in getSubOperand64()
110   case AMDGPU::sub0:  in getSubOperand64()
112   case AMDGPU::sub1:  in getSubOperand64()
126   unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_ADD()
127   unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectG_ADD()
134   MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));  in selectG_ADD()
135   MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));  in selectG_ADD()
137   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)  in selectG_ADD()
141   MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));  in selectG_ADD()
142   MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));  in selectG_ADD()
144   BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)  in selectG_ADD()
148   BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())  in selectG_ADD()
150           .addImm(AMDGPU::sub0)  in selectG_ADD()
152           .addImm(AMDGPU::sub1);  in selectG_ADD()
157     RBI.constrainGenericRegister(MO.getReg(), AMDGPU::SReg_64RegClass, MRI);  in selectG_ADD()
206     BuildMI(*I.getParent(), &I, DL, TII.get(AMDGPU::COPY))  in selectG_INTRINSIC()
222   unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP;  in buildEXP()
264     unsigned Undef = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);  in selectG_INTRINSIC_W_SIDE_EFFECTS()
268     BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);  in selectG_INTRINSIC_W_SIDE_EFFECTS()
292     Opcode = AMDGPU::FLAT_STORE_DWORD;  in selectG_STORE()
295     Opcode = AMDGPU::FLAT_STORE_DWORDX2;  in selectG_STORE()
298     Opcode = AMDGPU::FLAT_STORE_DWORDX3;  in selectG_STORE()
301     Opcode = AMDGPU::FLAT_STORE_DWORDX4;  in selectG_STORE()
340     IsSgpr = RB->getID() == AMDGPU::SGPRRegBankID;  in selectG_CONSTANT()
351   unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;  in selectG_CONSTANT()
359   const TargetRegisterClass *RC = IsSgpr ? &AMDGPU::SReg_32_XM0RegClass :  in selectG_CONSTANT()
360                                            &AMDGPU::VGPR_32RegClass;  in selectG_CONSTANT()
372       BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)  in selectG_CONSTANT()
374               .addImm(AMDGPU::sub0)  in selectG_CONSTANT()
376               .addImm(AMDGPU::sub1);  in selectG_CONSTANT()
416     if (OpBank->getID() == AMDGPU::SGPRRegBankID)  in getAddrModeInfo()
454   case AMDGPU::S_LOAD_DWORD_IMM:  in getSmrdOpcode()
457       return AMDGPU::S_LOAD_DWORDX2_IMM;  in getSmrdOpcode()
459       return AMDGPU::S_LOAD_DWORDX4_IMM;  in getSmrdOpcode()
461       return AMDGPU::S_LOAD_DWORDX8_IMM;  in getSmrdOpcode()
463       return AMDGPU::S_LOAD_DWORDX16_IMM;  in getSmrdOpcode()
466   case AMDGPU::S_LOAD_DWORD_IMM_ci:  in getSmrdOpcode()
469       return AMDGPU::S_LOAD_DWORDX2_IMM_ci;  in getSmrdOpcode()
471       return AMDGPU::S_LOAD_DWORDX4_IMM_ci;  in getSmrdOpcode()
473       return AMDGPU::S_LOAD_DWORDX8_IMM_ci;  in getSmrdOpcode()
475       return AMDGPU::S_LOAD_DWORDX16_IMM_ci;  in getSmrdOpcode()
478   case AMDGPU::S_LOAD_DWORD_SGPR:  in getSmrdOpcode()
481       return AMDGPU::S_LOAD_DWORDX2_SGPR;  in getSmrdOpcode()
483       return AMDGPU::S_LOAD_DWORDX4_SGPR;  in getSmrdOpcode()
485       return AMDGPU::S_LOAD_DWORDX8_SGPR;  in getSmrdOpcode()
487       return AMDGPU::S_LOAD_DWORDX16_SGPR;  in getSmrdOpcode()
532     int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(Subtarget, GEPInfo.Imm);  in selectSMRD()
533     if (AMDGPU::isLegalSMRDImmOffset(Subtarget, GEPInfo.Imm)) {  in selectSMRD()
534       Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);  in selectSMRD()
545       Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM_ci, LoadSize);  in selectSMRD()
554       Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_SGPR, LoadSize);  in selectSMRD()
555       unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);  in selectSMRD()
556       BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B32), OffsetReg)  in selectSMRD()
568   Opcode = getSmrdOpcode(AMDGPU::S_LOAD_DWORD_IMM, LoadSize);  in selectSMRD()
600     Opcode = AMDGPU::FLAT_LOAD_DWORD;  in selectG_LOAD()
603     Opcode = AMDGPU::FLAT_LOAD_DWORDX2;  in selectG_LOAD()