129   assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());  in setImpSCCDefDead()
143       U->getOpcode() != AMDGPU::SI_END_CF)  in isSimpleIf()
176   assert(SaveExec.getSubReg() == AMDGPU::NoSubRegister &&  in emitIf()
177          Cond.getSubReg() == AMDGPU::NoSubRegister);  in emitIf()
182   assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());  in emitIf()
192                        : MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in emitIf()
194     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)  in emitIf()
195     .addReg(AMDGPU::EXEC)  in emitIf()
196     .addReg(AMDGPU::EXEC, RegState::ImplicitDefine);  in emitIf()
198   unsigned Tmp = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in emitIf()
201     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B64), Tmp)  in emitIf()
210       BuildMI(MBB, I, DL, TII->get(AMDGPU::S_XOR_B64), SaveExecReg)  in emitIf()
219     BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64_term), AMDGPU::EXEC)  in emitIf()
224   MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))  in emitIf()
243   LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC, TRI));  in emitIf()
261   assert(MI.getOperand(0).getSubReg() == AMDGPU::NoSubRegister);  in emitElse()
269   unsigned CopyReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);  in emitElse()
271     BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)  in emitElse()
277     MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass) : DstReg;  in emitElse()
279     BuildMI(MBB, Start, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), SaveReg)  in emitElse()
288       BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_AND_B64), DstReg)  in emitElse()
289       .addReg(AMDGPU::EXEC)  in emitElse()
297     BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC)  in emitElse()
298     .addReg(AMDGPU::EXEC)  in emitElse()
302     BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))  in emitElse()
327   LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::EXEC, TRI));  in emitElse()
351     And = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64), Dst)  in emitIfBreak()
352              .addReg(AMDGPU::EXEC)  in emitIfBreak()
354     Or = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)  in emitIfBreak()
358     Or = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)  in emitIfBreak()
376       BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64_term), AMDGPU::EXEC)  in emitLoop()
377           .addReg(AMDGPU::EXEC)  in emitLoop()
381       BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))  in emitLoop()
398       BuildMI(MBB, InsPt, DL, TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)  in emitEndCf()
399           .addReg(AMDGPU::EXEC)  in emitEndCf()
430     if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&  in findMaskOperands()
431         !(I->isCopy() && I->getOperand(0).getReg() != AMDGPU::EXEC))  in findMaskOperands()
437         SrcOp.getReg() == AMDGPU::EXEC))  in findMaskOperands()
489       case AMDGPU::SI_IF:  in runOnMachineFunction()
493       case AMDGPU::SI_ELSE:  in runOnMachineFunction()
497       case AMDGPU::SI_IF_BREAK:  in runOnMachineFunction()
501       case AMDGPU::SI_LOOP:  in runOnMachineFunction()
505       case AMDGPU::SI_END_CF:  in runOnMachineFunction()
509       case AMDGPU::S_AND_B64:  in runOnMachineFunction()
510       case AMDGPU::S_OR_B64:  in runOnMachineFunction()