Lines Matching refs:AMDGPU
79 classifyPressureSet(i, AMDGPU::SGPR0, SGPRPressureSets); in SIRegisterInfo()
80 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); in SIRegisterInfo()
114 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg()
115 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass); in reservedPrivateSegmentBufferReg()
139 return AMDGPU::SGPR_32RegClass.getRegister(Reg); in reservedPrivateSegmentWaveByteOffsetReg()
144 return AMDGPU::SGPR32; in reservedStackPtrOffsetReg()
152 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
153 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
156 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
159 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
160 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
161 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
162 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); in getReservedRegs()
165 reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK); in getReservedRegs()
168 reserveRegisterTuples(Reserved, AMDGPU::TBA); in getReservedRegs()
169 reserveRegisterTuples(Reserved, AMDGPU::TMA); in getReservedRegs()
170 reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1); in getReservedRegs()
171 reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3); in getReservedRegs()
172 reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5); in getReservedRegs()
173 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7); in getReservedRegs()
174 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9); in getReservedRegs()
175 reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11); in getReservedRegs()
176 reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13); in getReservedRegs()
177 reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15); in getReservedRegs()
182 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs(); in getReservedRegs()
184 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i); in getReservedRegs()
189 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs(); in getReservedRegs()
191 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i); in getReservedRegs()
198 if (ScratchWaveOffsetReg != AMDGPU::NoRegister) { in getReservedRegs()
204 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
217 if (StackPtrReg != AMDGPU::NoRegister) { in getReservedRegs()
223 if (FrameReg != AMDGPU::NoRegister) { in getReservedRegs()
277 int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getMUBUFInstrOffset()
278 AMDGPU::OpName::offset); in getMUBUFInstrOffset()
287 assert(Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
288 AMDGPU::OpName::vaddr) && in getFrameIndexInstrOffset()
318 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg) in materializeFrameBaseRegister()
324 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister()
326 unsigned FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
328 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
330 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg) in materializeFrameBaseRegister()
359 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in resolveFrameIndex()
362 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == in resolveFrameIndex()
367 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
391 return &AMDGPU::VGPR_32RegClass; in getPointerRegClass()
397 case AMDGPU::SI_SPILL_S512_SAVE: in getNumSubRegsForSpillOp()
398 case AMDGPU::SI_SPILL_S512_RESTORE: in getNumSubRegsForSpillOp()
399 case AMDGPU::SI_SPILL_V512_SAVE: in getNumSubRegsForSpillOp()
400 case AMDGPU::SI_SPILL_V512_RESTORE: in getNumSubRegsForSpillOp()
402 case AMDGPU::SI_SPILL_S256_SAVE: in getNumSubRegsForSpillOp()
403 case AMDGPU::SI_SPILL_S256_RESTORE: in getNumSubRegsForSpillOp()
404 case AMDGPU::SI_SPILL_V256_SAVE: in getNumSubRegsForSpillOp()
405 case AMDGPU::SI_SPILL_V256_RESTORE: in getNumSubRegsForSpillOp()
407 case AMDGPU::SI_SPILL_S128_SAVE: in getNumSubRegsForSpillOp()
408 case AMDGPU::SI_SPILL_S128_RESTORE: in getNumSubRegsForSpillOp()
409 case AMDGPU::SI_SPILL_V128_SAVE: in getNumSubRegsForSpillOp()
410 case AMDGPU::SI_SPILL_V128_RESTORE: in getNumSubRegsForSpillOp()
412 case AMDGPU::SI_SPILL_V96_SAVE: in getNumSubRegsForSpillOp()
413 case AMDGPU::SI_SPILL_V96_RESTORE: in getNumSubRegsForSpillOp()
415 case AMDGPU::SI_SPILL_S64_SAVE: in getNumSubRegsForSpillOp()
416 case AMDGPU::SI_SPILL_S64_RESTORE: in getNumSubRegsForSpillOp()
417 case AMDGPU::SI_SPILL_V64_SAVE: in getNumSubRegsForSpillOp()
418 case AMDGPU::SI_SPILL_V64_RESTORE: in getNumSubRegsForSpillOp()
420 case AMDGPU::SI_SPILL_S32_SAVE: in getNumSubRegsForSpillOp()
421 case AMDGPU::SI_SPILL_S32_RESTORE: in getNumSubRegsForSpillOp()
422 case AMDGPU::SI_SPILL_V32_SAVE: in getNumSubRegsForSpillOp()
423 case AMDGPU::SI_SPILL_V32_RESTORE: in getNumSubRegsForSpillOp()
431 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getOffsetMUBUFStore()
432 return AMDGPU::BUFFER_STORE_DWORD_OFFSET; in getOffsetMUBUFStore()
433 case AMDGPU::BUFFER_STORE_BYTE_OFFEN: in getOffsetMUBUFStore()
434 return AMDGPU::BUFFER_STORE_BYTE_OFFSET; in getOffsetMUBUFStore()
435 case AMDGPU::BUFFER_STORE_SHORT_OFFEN: in getOffsetMUBUFStore()
436 return AMDGPU::BUFFER_STORE_SHORT_OFFSET; in getOffsetMUBUFStore()
437 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN: in getOffsetMUBUFStore()
438 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET; in getOffsetMUBUFStore()
439 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN: in getOffsetMUBUFStore()
440 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET; in getOffsetMUBUFStore()
441 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN: in getOffsetMUBUFStore()
442 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET; in getOffsetMUBUFStore()
443 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN: in getOffsetMUBUFStore()
444 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET; in getOffsetMUBUFStore()
452 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getOffsetMUBUFLoad()
453 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in getOffsetMUBUFLoad()
454 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN: in getOffsetMUBUFLoad()
455 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET; in getOffsetMUBUFLoad()
456 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN: in getOffsetMUBUFLoad()
457 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET; in getOffsetMUBUFLoad()
458 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN: in getOffsetMUBUFLoad()
459 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET; in getOffsetMUBUFLoad()
460 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN: in getOffsetMUBUFLoad()
461 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET; in getOffsetMUBUFLoad()
462 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN: in getOffsetMUBUFLoad()
463 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET; in getOffsetMUBUFLoad()
464 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN: in getOffsetMUBUFLoad()
465 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET; in getOffsetMUBUFLoad()
466 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
467 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
468 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
469 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
470 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
471 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
472 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
473 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
474 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN: in getOffsetMUBUFLoad()
475 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET; in getOffsetMUBUFLoad()
476 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN: in getOffsetMUBUFLoad()
477 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET; in getOffsetMUBUFLoad()
500 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
504 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
505 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
513 AMDGPU::OpName::vdata_in); in buildMUBUFOffsetLoadStore()
544 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT); in buildSpillLoadStore()
555 SOffset = AMDGPU::NoRegister; in buildSpillLoadStore()
565 SOffset = RS->FindUnusedReg(&AMDGPU::SGPR_32RegClass); in buildSpillLoadStore()
567 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
581 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset) in buildSpillLoadStore()
621 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffsetReg) in buildSpillLoadStore()
630 return { 16, Store ? AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR : in getSpillEltSize()
631 AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR }; in getSpillEltSize()
635 return { 8, Store ? AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR : in getSpillEltSize()
636 AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR }; in getSpillEltSize()
639 return { 4, Store ? AMDGPU::S_BUFFER_STORE_DWORD_SGPR : in getSpillEltSize()
640 AMDGPU::S_BUFFER_LOAD_DWORD_SGPR}; in getSpillEltSize()
676 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in spillSGPR()
678 unsigned OffsetReg = AMDGPU::M0; in spillSGPR()
679 unsigned M0CopyReg = AMDGPU::NoRegister; in spillSGPR()
682 if (RS->isRegUsed(AMDGPU::M0)) { in spillSGPR()
683 M0CopyReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in spillSGPR()
684 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg) in spillSGPR()
685 .addReg(AMDGPU::M0); in spillSGPR()
730 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg) in spillSGPR()
734 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in spillSGPR()
761 TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32), in spillSGPR()
777 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in spillSGPR()
781 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in spillSGPR()
801 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE)) in spillSGPR()
811 if (M0CopyReg != AMDGPU::NoRegister) { in spillSGPR()
812 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0) in spillSGPR()
846 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in restoreSGPR()
848 unsigned OffsetReg = AMDGPU::M0; in restoreSGPR()
849 unsigned M0CopyReg = AMDGPU::NoRegister; in restoreSGPR()
852 if (RS->isRegUsed(AMDGPU::M0)) { in restoreSGPR()
853 M0CopyReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in restoreSGPR()
854 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg) in restoreSGPR()
855 .addReg(AMDGPU::M0); in restoreSGPR()
892 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg) in restoreSGPR()
896 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in restoreSGPR()
916 BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), in restoreSGPR()
929 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in restoreSGPR()
939 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) in restoreSGPR()
947 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) in restoreSGPR()
955 if (M0CopyReg != AMDGPU::NoRegister) { in restoreSGPR()
956 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0) in restoreSGPR()
972 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
973 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
974 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
975 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
976 case AMDGPU::SI_SPILL_S32_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
978 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
979 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
980 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
981 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
982 case AMDGPU::SI_SPILL_S32_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1006 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateFrameIndex()
1007 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateFrameIndex()
1008 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateFrameIndex()
1009 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateFrameIndex()
1010 case AMDGPU::SI_SPILL_S32_SAVE: { in eliminateFrameIndex()
1016 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateFrameIndex()
1017 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateFrameIndex()
1018 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateFrameIndex()
1019 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateFrameIndex()
1020 case AMDGPU::SI_SPILL_S32_RESTORE: { in eliminateFrameIndex()
1026 case AMDGPU::SI_SPILL_V512_SAVE: in eliminateFrameIndex()
1027 case AMDGPU::SI_SPILL_V256_SAVE: in eliminateFrameIndex()
1028 case AMDGPU::SI_SPILL_V128_SAVE: in eliminateFrameIndex()
1029 case AMDGPU::SI_SPILL_V96_SAVE: in eliminateFrameIndex()
1030 case AMDGPU::SI_SPILL_V64_SAVE: in eliminateFrameIndex()
1031 case AMDGPU::SI_SPILL_V32_SAVE: { in eliminateFrameIndex()
1033 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1034 buildSpillLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET, in eliminateFrameIndex()
1037 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), in eliminateFrameIndex()
1038 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), in eliminateFrameIndex()
1039 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1046 case AMDGPU::SI_SPILL_V32_RESTORE: in eliminateFrameIndex()
1047 case AMDGPU::SI_SPILL_V64_RESTORE: in eliminateFrameIndex()
1048 case AMDGPU::SI_SPILL_V96_RESTORE: in eliminateFrameIndex()
1049 case AMDGPU::SI_SPILL_V128_RESTORE: in eliminateFrameIndex()
1050 case AMDGPU::SI_SPILL_V256_RESTORE: in eliminateFrameIndex()
1051 case AMDGPU::SI_SPILL_V512_RESTORE: { in eliminateFrameIndex()
1053 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1055 buildSpillLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET, in eliminateFrameIndex()
1058 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), in eliminateFrameIndex()
1059 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), in eliminateFrameIndex()
1060 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1080 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in eliminateFrameIndex()
1082 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
1085 MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex()
1087 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), DiffReg) in eliminateFrameIndex()
1094 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg) in eliminateFrameIndex()
1099 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex()
1101 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ScaledReg) in eliminateFrameIndex()
1106 if (AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) { in eliminateFrameIndex()
1112 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in eliminateFrameIndex()
1114 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg) in eliminateFrameIndex()
1133 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
1134 AMDGPU::OpName::vaddr)); in eliminateFrameIndex()
1136 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() in eliminateFrameIndex()
1141 = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(); in eliminateFrameIndex()
1157 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex()
1158 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1177 REG_RANGE(AMDGPU::VGPR0, AMDGPU::VGPR255, VGPR32RegNames); in getRegAsmName()
1178 REG_RANGE(AMDGPU::SGPR0, AMDGPU::SGPR103, SGPR32RegNames); in getRegAsmName()
1179 REG_RANGE(AMDGPU::VGPR0_VGPR1, AMDGPU::VGPR254_VGPR255, VGPR64RegNames); in getRegAsmName()
1180 REG_RANGE(AMDGPU::SGPR0_SGPR1, AMDGPU::SGPR102_SGPR103, SGPR64RegNames); in getRegAsmName()
1181 REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2, AMDGPU::VGPR253_VGPR254_VGPR255, in getRegAsmName()
1184 REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3, in getRegAsmName()
1185 AMDGPU::VGPR252_VGPR253_VGPR254_VGPR255, in getRegAsmName()
1187 REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, in getRegAsmName()
1188 AMDGPU::SGPR100_SGPR101_SGPR102_SGPR103, in getRegAsmName()
1191 REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7, in getRegAsmName()
1192 AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255, in getRegAsmName()
1196 …AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VG… in getRegAsmName()
1197 …AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VG… in getRegAsmName()
1200 REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7, in getRegAsmName()
1201 AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103, in getRegAsmName()
1205 …AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SG… in getRegAsmName()
1206 …AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99_SGPR10… in getRegAsmName()
1214 case AMDGPU::FLAT_SCR: in getRegAsmName()
1216 case AMDGPU::FLAT_SCR_LO: in getRegAsmName()
1218 case AMDGPU::FLAT_SCR_HI: in getRegAsmName()
1232 &AMDGPU::VGPR_32RegClass, in getPhysRegClass()
1233 &AMDGPU::SReg_32RegClass, in getPhysRegClass()
1234 &AMDGPU::VReg_64RegClass, in getPhysRegClass()
1235 &AMDGPU::SReg_64RegClass, in getPhysRegClass()
1236 &AMDGPU::VReg_96RegClass, in getPhysRegClass()
1237 &AMDGPU::VReg_128RegClass, in getPhysRegClass()
1238 &AMDGPU::SReg_128RegClass, in getPhysRegClass()
1239 &AMDGPU::VReg_256RegClass, in getPhysRegClass()
1240 &AMDGPU::SReg_256RegClass, in getPhysRegClass()
1241 &AMDGPU::VReg_512RegClass, in getPhysRegClass()
1242 &AMDGPU::SReg_512RegClass, in getPhysRegClass()
1243 &AMDGPU::SCC_CLASSRegClass, in getPhysRegClass()
1244 &AMDGPU::Pseudo_SReg_32RegClass, in getPhysRegClass()
1245 &AMDGPU::Pseudo_SReg_128RegClass, in getPhysRegClass()
1264 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr; in hasVGPRs()
1266 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr; in hasVGPRs()
1268 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr; in hasVGPRs()
1270 return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr; in hasVGPRs()
1272 return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr; in hasVGPRs()
1274 return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr; in hasVGPRs()
1284 return &AMDGPU::VGPR_32RegClass; in getEquivalentVGPRClass()
1286 return &AMDGPU::VReg_64RegClass; in getEquivalentVGPRClass()
1288 return &AMDGPU::VReg_96RegClass; in getEquivalentVGPRClass()
1290 return &AMDGPU::VReg_128RegClass; in getEquivalentVGPRClass()
1292 return &AMDGPU::VReg_256RegClass; in getEquivalentVGPRClass()
1294 return &AMDGPU::VReg_512RegClass; in getEquivalentVGPRClass()
1304 return &AMDGPU::SGPR_32RegClass; in getEquivalentSGPRClass()
1306 return &AMDGPU::SReg_64RegClass; in getEquivalentSGPRClass()
1308 return &AMDGPU::SReg_128RegClass; in getEquivalentSGPRClass()
1310 return &AMDGPU::SReg_256RegClass; in getEquivalentSGPRClass()
1312 return &AMDGPU::SReg_512RegClass; in getEquivalentSGPRClass()
1320 if (SubIdx == AMDGPU::NoSubRegister) in getSubRegClass()
1328 return &AMDGPU::SGPR_32RegClass; in getSubRegClass()
1330 return &AMDGPU::SReg_64RegClass; in getSubRegClass()
1332 return &AMDGPU::SReg_128RegClass; in getSubRegClass()
1334 return &AMDGPU::SReg_256RegClass; in getSubRegClass()
1342 return &AMDGPU::VGPR_32RegClass; in getSubRegClass()
1344 return &AMDGPU::VReg_64RegClass; in getSubRegClass()
1346 return &AMDGPU::VReg_96RegClass; in getSubRegClass()
1348 return &AMDGPU::VReg_128RegClass; in getSubRegClass()
1350 return &AMDGPU::VReg_256RegClass; in getSubRegClass()
1393 return AMDGPU::NoRegister; in findUnusedRegister()
1400 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1401 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in getRegSplitParts()
1402 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in getRegSplitParts()
1403 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in getRegSplitParts()
1407 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1408 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in getRegSplitParts()
1412 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1416 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, in getRegSplitParts()
1420 AMDGPU::sub0, AMDGPU::sub1, in getRegSplitParts()
1423 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()
1443 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in getRegSplitParts()
1444 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, in getRegSplitParts()
1445 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, in getRegSplitParts()
1446 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15 in getRegSplitParts()
1450 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in getRegSplitParts()
1451 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7 in getRegSplitParts()
1456 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3 in getRegSplitParts()
1459 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()
1476 AMDGPU::sub0_sub1_sub2_sub3, in getRegSplitParts()
1477 AMDGPU::sub4_sub5_sub6_sub7, in getRegSplitParts()
1478 AMDGPU::sub8_sub9_sub10_sub11, in getRegSplitParts()
1479 AMDGPU::sub12_sub13_sub14_sub15 in getRegSplitParts()
1483 AMDGPU::sub0_sub1_sub2_sub3, in getRegSplitParts()
1484 AMDGPU::sub4_sub5_sub6_sub7 in getRegSplitParts()
1487 switch (AMDGPU::getRegBitWidth(*RC->MC)) { in getRegSplitParts()
1547 case AMDGPU::VGPR_32RegClassID: in getRegPressureLimit()
1549 case AMDGPU::SGPR_32RegClassID: in getRegPressureLimit()
1557 return getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in getRegPressureSetLimit()
1561 return getRegPressureLimit(&AMDGPU::SGPR_32RegClass, in getRegPressureSetLimit()
1570 if (hasRegUnit(AMDGPU::M0, RegUnit)) in getRegUnitPressureSets()
1577 return AMDGPU::SGPR30_SGPR31; in getReturnAddressReg()
1590 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass : in getConstrainedRegClassForOperand()
1591 &AMDGPU::SReg_32_XM0RegClass; in getConstrainedRegClassForOperand()
1593 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass : in getConstrainedRegClassForOperand()
1594 &AMDGPU::SReg_64_XEXECRegClass; in getConstrainedRegClassForOperand()
1596 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass : in getConstrainedRegClassForOperand()
1599 return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass : in getConstrainedRegClassForOperand()
1600 &AMDGPU::SReg_128RegClass; in getConstrainedRegClassForOperand()