28 using namespace llvm::AMDGPU;
212   if (STI.hasFeature(AMDGPU::FeatureR128A16))  in printR128A16()
254   case AMDGPU::VCC:  in printRegOperand()
257   case AMDGPU::SCC:  in printRegOperand()
260   case AMDGPU::EXEC:  in printRegOperand()
263   case AMDGPU::M0:  in printRegOperand()
266   case AMDGPU::FLAT_SCR:  in printRegOperand()
269   case AMDGPU::XNACK_MASK:  in printRegOperand()
272   case AMDGPU::VCC_LO:  in printRegOperand()
275   case AMDGPU::VCC_HI:  in printRegOperand()
278   case AMDGPU::TBA_LO:  in printRegOperand()
281   case AMDGPU::TBA_HI:  in printRegOperand()
284   case AMDGPU::TMA_LO:  in printRegOperand()
287   case AMDGPU::TMA_HI:  in printRegOperand()
290   case AMDGPU::EXEC_LO:  in printRegOperand()
293   case AMDGPU::EXEC_HI:  in printRegOperand()
296   case AMDGPU::FLAT_SCR_LO:  in printRegOperand()
299   case AMDGPU::FLAT_SCR_HI:  in printRegOperand()
302   case AMDGPU::XNACK_MASK_LO:  in printRegOperand()
305   case AMDGPU::XNACK_MASK_HI:  in printRegOperand()
308   case AMDGPU::FP_REG:  in printRegOperand()
309   case AMDGPU::SP_REG:  in printRegOperand()
310   case AMDGPU::SCRATCH_WAVE_OFFSET_REG:  in printRegOperand()
311   case AMDGPU::PRIVATE_RSRC_REG:  in printRegOperand()
322   if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(RegNo)) {  in printRegOperand()
325   } else  if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(RegNo)) {  in printRegOperand()
328   } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo)) {  in printRegOperand()
331   } else  if (MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo)) {  in printRegOperand()
334   } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(RegNo)) {  in printRegOperand()
337   } else  if (MRI.getRegClass(AMDGPU::SGPR_128RegClassID).contains(RegNo)) {  in printRegOperand()
340   } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(RegNo)) {  in printRegOperand()
343   } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(RegNo)) {  in printRegOperand()
346   } else if (MRI.getRegClass(AMDGPU::SGPR_256RegClassID).contains(RegNo)) {  in printRegOperand()
349   } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(RegNo)) {  in printRegOperand()
352   } else if (MRI.getRegClass(AMDGPU::SGPR_512RegClassID).contains(RegNo)) {  in printRegOperand()
384   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))  in printVINTRPDst()
418     assert(STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]);  in printImmediate16()
459            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in printImmediate32()
493            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in printImmediate64()
518     case AMDGPU::OPERAND_REG_IMM_INT32:  in printOperand()
519     case AMDGPU::OPERAND_REG_IMM_FP32:  in printOperand()
520     case AMDGPU::OPERAND_REG_INLINE_C_INT32:  in printOperand()
521     case AMDGPU::OPERAND_REG_INLINE_C_FP32:  in printOperand()
525     case AMDGPU::OPERAND_REG_IMM_INT64:  in printOperand()
526     case AMDGPU::OPERAND_REG_IMM_FP64:  in printOperand()
527     case AMDGPU::OPERAND_REG_INLINE_C_INT64:  in printOperand()
528     case AMDGPU::OPERAND_REG_INLINE_C_FP64:  in printOperand()
531     case AMDGPU::OPERAND_REG_INLINE_C_INT16:  in printOperand()
532     case AMDGPU::OPERAND_REG_INLINE_C_FP16:  in printOperand()
533     case AMDGPU::OPERAND_REG_IMM_INT16:  in printOperand()
534     case AMDGPU::OPERAND_REG_IMM_FP16:  in printOperand()
537     case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:  in printOperand()
538     case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:  in printOperand()
562       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));  in printOperand()
628   using namespace AMDGPU::DPP;  in printDPPCtrl()
695   using namespace llvm::AMDGPU::SDWA;  in printSDWASel()
734   using namespace llvm::AMDGPU::SDWA;  in printSDWADstUnused()
751   int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);  in printExpSrcN()
754   int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);  in printExpSrcN()
839   for (int OpName : { AMDGPU::OpName::src0_modifiers,  in printPackedModifier()
840                       AMDGPU::OpName::src1_modifiers,  in printPackedModifier()
841                       AMDGPU::OpName::src2_modifiers }) {  in printPackedModifier()
842     int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);  in printPackedModifier()
1011   using namespace llvm::AMDGPU::SendMsg;  in printSendMsg()
1053   using namespace llvm::AMDGPU::Swizzle;  in printSwizzleBitmask()
1085   using namespace llvm::AMDGPU::Swizzle;  in printSwizzle()
1158   AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU());  in printWaitFlag()
1187   using namespace llvm::AMDGPU::Hwreg;  in printHwreg()
1196   if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI) || AMDGPU::isVI(STI))  in printHwreg()