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Searched refs:RISCV (Results 1 – 25 of 149) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSExtWRemoval.cpp92 if (opcode == RISCV::LD || opcode == RISCV::LWU) in isAllUsesReadW()
198 case RISCV::LUI: in isSignExtendingOpW()
199 case RISCV::LW: in isSignExtendingOpW()
229 case RISCV::LBU: in isSignExtendingOpW()
230 case RISCV::LHU: in isSignExtendingOpW()
231 case RISCV::LB: in isSignExtendingOpW()
232 case RISCV::LH: in isSignExtendingOpW()
233 case RISCV::SLT: in isSignExtendingOpW()
243 case RISCV::CLZ: in isSignExtendingOpW()
280 case RISCV::LD: in isSignExtendingOpW()
[all …]
H A DRISCVInsertVSETVLI.cpp59 case RISCV::PseudoVMV_S_X_M1: in isScalarMoveInstr()
60 case RISCV::PseudoVMV_S_X_M2: in isScalarMoveInstr()
61 case RISCV::PseudoVMV_S_X_M4: in isScalarMoveInstr()
62 case RISCV::PseudoVMV_S_X_M8: in isScalarMoveInstr()
91 case RISCV::PseudoVLE8_V_M1: in getEEWForLoadStore()
93 case RISCV::PseudoVLE8_V_M2: in getEEWForLoadStore()
95 case RISCV::PseudoVLE8_V_M4: in getEEWForLoadStore()
97 case RISCV::PseudoVLE8_V_M8: in getEEWForLoadStore()
119 case RISCV::PseudoVSE8_V_M1: in getEEWForLoadStore()
121 case RISCV::PseudoVSE8_V_M2: in getEEWForLoadStore()
[all …]
H A DRISCVExpandPseudoInsts.cpp99 case RISCV::PseudoLLA: in expandMI()
101 case RISCV::PseudoLA: in expandMI()
107 case RISCV::PseudoVSETVLI: in expandMI()
215 SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadAddress()
230 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW; in expandLoadTLSIEAddress()
301 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in expandVSPILL()
306 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in expandVSPILL()
311 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in expandVSPILL()
351 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in expandVRELOAD()
356 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in expandVRELOAD()
[all …]
H A DRISCVInstrInfo.cpp74 case RISCV::LB: in isLoadFromStackSlot()
75 case RISCV::LBU: in isLoadFromStackSlot()
76 case RISCV::LH: in isLoadFromStackSlot()
79 case RISCV::LW: in isLoadFromStackSlot()
82 case RISCV::LD: in isLoadFromStackSlot()
101 case RISCV::SB: in isStoreToStackSlot()
102 case RISCV::SH: in isStoreToStackSlot()
103 case RISCV::SW: in isStoreToStackSlot()
106 case RISCV::SD: in isStoreToStackSlot()
471 RISCV::SW : RISCV::SD; in storeRegToStackSlot()
[all …]
H A DRISCVRegisterInfo.cpp32 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
33 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
34 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
37 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
38 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
41 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
43 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
44 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
121 return PhysReg == RISCV::X0 || PhysReg == RISCV::VLENB; in isConstantPhysReg()
[all …]
H A DRISCVMakeCompressible.cpp104 case RISCV::LW: in log2LdstWidth()
105 case RISCV::SW: in log2LdstWidth()
106 case RISCV::FLW: in log2LdstWidth()
107 case RISCV::FSW: in log2LdstWidth()
109 case RISCV::LD: in log2LdstWidth()
110 case RISCV::SD: in log2LdstWidth()
111 case RISCV::FLD: in log2LdstWidth()
112 case RISCV::FSD: in log2LdstWidth()
150 return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) || in isCompressibleLoad()
151 Opcode == RISCV::LD || Opcode == RISCV::FLD; in isCompressibleLoad()
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H A DRISCVMergeBaseOffset.cpp329 case RISCV::LB: in detectAndFoldOffset()
330 case RISCV::LH: in detectAndFoldOffset()
331 case RISCV::LW: in detectAndFoldOffset()
332 case RISCV::LBU: in detectAndFoldOffset()
333 case RISCV::LHU: in detectAndFoldOffset()
334 case RISCV::LWU: in detectAndFoldOffset()
335 case RISCV::LD: in detectAndFoldOffset()
339 case RISCV::SB: in detectAndFoldOffset()
340 case RISCV::SH: in detectAndFoldOffset()
341 case RISCV::SW: in detectAndFoldOffset()
[all …]
H A DRISCVExpandAtomicPseudoInsts.cpp137 return RISCV::LR_W; in getLRForRMW32()
141 return RISCV::LR_W; in getLRForRMW32()
154 return RISCV::SC_W; in getSCForRMW32()
156 return RISCV::SC_W; in getSCForRMW32()
171 return RISCV::LR_D; in getLRForRMW64()
175 return RISCV::LR_D; in getLRForRMW64()
188 return RISCV::SC_D; in getSCForRMW64()
190 return RISCV::SC_D; in getSCForRMW64()
252 .addReg(RISCV::X0) in doAtomicBinOpExpansion()
337 .addReg(RISCV::X0) in doMaskedAtomicBinOpExpansion()
[all …]
H A DRISCVISelDAGToDAG.cpp31 namespace RISCV { namespace
198 RISCV::VRN2M1RegClassID, RISCV::VRN3M1RegClassID, RISCV::VRN4M1RegClassID, in createTuple()
199 RISCV::VRN5M1RegClassID, RISCV::VRN6M1RegClassID, RISCV::VRN7M1RegClassID, in createTuple()
418 const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( in selectVLXSEG()
459 const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo( in selectVSSEG()
1716 const RISCV::VLEPseudo *P = RISCV::getVLEPseudo( in Select()
2373 case RISCV::ADD: Opc = RISCV::ADDW; break; in doPeepholeSExtW()
2374 case RISCV::ADDI: Opc = RISCV::ADDIW; break; in doPeepholeSExtW()
2375 case RISCV::SUB: Opc = RISCV::SUBW; break; in doPeepholeSExtW()
2376 case RISCV::MUL: Opc = RISCV::MULW; break; in doPeepholeSExtW()
[all …]
H A DRISCVFrameLowering.cpp69 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
119 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
333 unsigned Opc = RISCV::ADD; in adjustReg()
336 Opc = RISCV::SUB; in adjustReg()
380 Opc = RISCV::SUB; in adjustStackForRVV()
716 FrameReg = RISCV::X2; in getFrameIndexReference()
878 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ in determineCalleeSaves()
879 RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */ in determineCalleeSaves()
880 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, in determineCalleeSaves()
881 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */ in determineCalleeSaves()
[all …]
H A DRISCVMCInstLower.cpp162 bool hasVLOutput = RISCV::isFaultFirstLoad(*MI); in lowerRISCVVMachineInstrToMCInst()
182 if (RISCV::VRM2RegClass.contains(Reg) || in lowerRISCVVMachineInstrToMCInst()
183 RISCV::VRM4RegClass.contains(Reg) || in lowerRISCVVMachineInstrToMCInst()
184 RISCV::VRM8RegClass.contains(Reg)) { in lowerRISCVVMachineInstrToMCInst()
185 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0); in lowerRISCVVMachineInstrToMCInst()
188 Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass); in lowerRISCVVMachineInstrToMCInst()
191 Reg = TRI->getSubReg(Reg, RISCV::sub_32); in lowerRISCVVMachineInstrToMCInst()
240 case RISCV::PseudoReadVLENB: in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
246 case RISCV::PseudoReadVL: in lowerRISCVMachineInstrToMCInst()
[all …]
H A DRISCVISelLowering.cpp10257 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
10258 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
10274 RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
10275 RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
10276 RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23};
10783 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, in CC_RISCV_FastCC()
10784 RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28, in CC_RISCV_FastCC()
10797 RISCV::F15_H, RISCV::F16_H, RISCV::F17_H, RISCV::F0_H, RISCV::F1_H, in CC_RISCV_FastCC()
10798 RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H, in CC_RISCV_FastCC()
10883 RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, in CC_RISCV_GHC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVELFObjectWriter.cpp77 case RISCV::fixup_riscv_jal: in getRelocType()
85 case RISCV::fixup_riscv_call: in getRelocType()
125 case RISCV::fixup_riscv_hi20: in getRelocType()
127 case RISCV::fixup_riscv_lo12_i: in getRelocType()
129 case RISCV::fixup_riscv_lo12_s: in getRelocType()
139 case RISCV::fixup_riscv_relax: in getRelocType()
141 case RISCV::fixup_riscv_align: in getRelocType()
143 case RISCV::fixup_riscv_set_6b: in getRelocType()
147 case RISCV::fixup_riscv_add_8: in getRelocType()
149 case RISCV::fixup_riscv_set_8: in getRelocType()
[all …]
H A DRISCVMatInt.cpp24 case RISCV::SLLI: in getInstSeqCost()
25 case RISCV::SRLI: in getInstSeqCost()
28 case RISCV::ADDI: in getInstSeqCost()
29 case RISCV::ADDIW: in getInstSeqCost()
30 case RISCV::LUI: in getInstSeqCost()
68 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
402 case RISCV::LUI: in getOpndKind()
410 case RISCV::ADDI: in getOpndKind()
412 case RISCV::SLLI: in getOpndKind()
413 case RISCV::SRLI: in getOpndKind()
[all …]
H A DRISCVAsmBackend.cpp175 case RISCV::C_BEQZ: in relaxInstruction()
182 case RISCV::C_BNEZ: in relaxInstruction()
189 case RISCV::C_J: in relaxInstruction()
195 case RISCV::C_JAL: in relaxInstruction()
253 Fixup = {RISCV::fixup_riscv_add_16, RISCV::fixup_riscv_sub_16}; in relaxDwarfLineAddr()
313 AddFixups(0, {RISCV::fixup_riscv_set_6b, RISCV::fixup_riscv_sub_6b}); in relaxDwarfCFA()
317 AddFixups(1, {RISCV::fixup_riscv_set_8, RISCV::fixup_riscv_sub_8}); in relaxDwarfCFA()
321 AddFixups(1, {RISCV::fixup_riscv_set_16, RISCV::fixup_riscv_sub_16}); in relaxDwarfCFA()
340 case RISCV::C_BEQZ: in getRelaxedOpcode()
342 case RISCV::C_BNEZ: in getRelaxedOpcode()
[all …]
H A DRISCVMCCodeEmitter.cpp109 if (MI.getOpcode() == RISCV::PseudoTAIL) { in expandFunctionCall()
111 Ra = RISCV::X6; in expandFunctionCall()
117 Ra = RISCV::X1; in expandFunctionCall()
134 MI.getOpcode() == RISCV::PseudoJump) in expandFunctionCall()
136 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
272 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; in getImmOpValue()
299 FixupKind = RISCV::fixup_riscv_hi20; in getImmOpValue()
340 FixupKind = RISCV::fixup_riscv_call; in getImmOpValue()
351 FixupKind = RISCV::fixup_riscv_jal; in getImmOpValue()
390 case RISCV::V0: in getVMaskReg()
[all …]
H A DRISCVBaseInfo.cpp24 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
41 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()
88 MCRegister getBPReg() { return RISCV::X9; } in getBPReg()
91 MCRegister getSCSPReg() { return RISCV::X18; } in getSCSPReg()
98 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()
100 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) in validate()
102 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
H A DRISCVELFStreamer.cpp158 if (Features[RISCV::FeatureStdExtC]) in finish()
195 return std::make_pair(RISCV::fixup_riscv_add_8, RISCV::fixup_riscv_sub_8); in getRelocPairForSize()
197 return std::make_pair(RISCV::fixup_riscv_add_16, in getRelocPairForSize()
198 RISCV::fixup_riscv_sub_16); in getRelocPairForSize()
200 return std::make_pair(RISCV::fixup_riscv_add_32, in getRelocPairForSize()
201 RISCV::fixup_riscv_sub_32); in getRelocPairForSize()
203 return std::make_pair(RISCV::fixup_riscv_add_64, in getRelocPairForSize()
204 RISCV::fixup_riscv_sub_64); in getRelocPairForSize()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp999 return Reg - RISCV::F0_D + RISCV::F0_H; in convertFPR64ToFPR16()
1004 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32()
1299 assert(!(RegNo >= RISCV::F0_H && RegNo <= RISCV::F31_H)); in matchRegisterNameHelper()
1300 assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F)); in matchRegisterNameHelper()
1306 if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31) in matchRegisterNameHelper()
2396 SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadAddress()
2415 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadTLSIEAddress()
2466 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
2616 if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || in validateInstruction()
2617 Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || in validateInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp71 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
82 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
157 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
168 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRPF64RegisterClass()
179 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
197 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
237 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
252 Reg = RISCV::V0; in decodeVMaskReg()
265 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP || in addImplySP()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dreg-usage.ll26 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
27 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
29 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 1 registers
31 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
32 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
34 ; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 2 registers
36 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::GPRRC, 2 registers
37 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
39 ; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 4 registers
42 ; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: RISCV::VRRC, 8 registers
[all …]
/llvm-project-15.0.7/clang/lib/Basic/Targets/
H A DRISCV.cpp211 return llvm::makeArrayRef(BuiltinInfo, clang::RISCV::LastTSBuiltin - in getTargetBuiltins()
289 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), in isValidCPUName()
295 llvm::RISCV::fillValidCPUArchList(Values, false); in fillValidCPUList()
299 return llvm::RISCV::checkTuneCPUKind( in isValidTuneCPUName()
300 llvm::RISCV::parseTuneCPUKind(Name, false), in isValidTuneCPUName()
306 llvm::RISCV::fillValidTuneCPUArchList(Values, false); in fillValidTuneCPUList()
310 return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), in isValidCPUName()
316 llvm::RISCV::fillValidCPUArchList(Values, true); in fillValidCPUList()
320 return llvm::RISCV::checkTuneCPUKind( in isValidTuneCPUName()
321 llvm::RISCV::parseTuneCPUKind(Name, true), in isValidTuneCPUName()
[all …]
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/
H A DBUILD.gn6 td_file = "../RISCV.td"
12 td_file = "../RISCV.td"
18 td_file = "../RISCV.td"
24 td_file = "../RISCV.td"
30 td_file = "../RISCV.td"
36 td_file = "../RISCV.td"
60 "//llvm/lib/Target/RISCV:RISCVGenCompressInstEmitter",
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/
H A DBUILD.gn3 # RISCV is the only target that has a "compress instr emitter", and it's
14 td_file = "RISCV.td"
20 td_file = "RISCV.td"
26 td_file = "RISCV.td"
32 td_file = "RISCV.td"
38 td_file = "RISCV.td"
95 # having the directory's name, "//llvm/lib/Target/RISCV" will refer to this
100 group("RISCV") {
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/
H A DBUILD.gn6 "//llvm/lib/Target/RISCV:LLVMRISCVCodeGen",
9 td_file = "../RISCV.td"
19 "//llvm/lib/Target/RISCV:RISCVGenCompressInstEmitter",
20 "//llvm/lib/Target/RISCV/MCTargetDesc",

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