32 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
33 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
34 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
37 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
38 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
40 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
41 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
43 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
44 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
47     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,  in RISCVRegisterInfo()
89   markSuperRegs(Reserved, RISCV::X0); // zero  in getReservedRegs()
90   markSuperRegs(Reserved, RISCV::X2); // sp  in getReservedRegs()
91   markSuperRegs(Reserved, RISCV::X3); // gp  in getReservedRegs()
92   markSuperRegs(Reserved, RISCV::X4); // tp  in getReservedRegs()
94     markSuperRegs(Reserved, RISCV::X8); // fp  in getReservedRegs()
101   markSuperRegs(Reserved, RISCV::VL);  in getReservedRegs()
102   markSuperRegs(Reserved, RISCV::VTYPE);  in getReservedRegs()
103   markSuperRegs(Reserved, RISCV::VXSAT);  in getReservedRegs()
104   markSuperRegs(Reserved, RISCV::VXRM);  in getReservedRegs()
105   markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)  in getReservedRegs()
108   markSuperRegs(Reserved, RISCV::FRM);  in getReservedRegs()
109   markSuperRegs(Reserved, RISCV::FFLAGS);  in getReservedRegs()
121   return PhysReg == RISCV::X0 || PhysReg == RISCV::VLENB;  in isConstantPhysReg()
131   {/*ra*/  RISCV::X1,   -1},
132   {/*s0*/  RISCV::X8,   -2},
133   {/*s1*/  RISCV::X9,   -3},
134   {/*s2*/  RISCV::X18,  -4},
135   {/*s3*/  RISCV::X19,  -5},
136   {/*s4*/  RISCV::X20,  -6},
137   {/*s5*/  RISCV::X21,  -7},
138   {/*s6*/  RISCV::X22,  -8},
139   {/*s7*/  RISCV::X23,  -9},
140   {/*s8*/  RISCV::X24,  -10},
141   {/*s9*/  RISCV::X25,  -11},
142   {/*s10*/ RISCV::X26,  -12},
143   {/*s11*/ RISCV::X27,  -13}
177   bool IsRVVSpill = RISCV::isRVVSpill(MI);  in eliminateFrameIndex()
195   unsigned ScalableAdjOpc = RISCV::ADD;  in eliminateFrameIndex()
200       ScalableAdjOpc = RISCV::SUB;  in eliminateFrameIndex()
210     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);  in eliminateFrameIndex()
212     if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {  in eliminateFrameIndex()
213       BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())  in eliminateFrameIndex()
219     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)  in eliminateFrameIndex()
235         Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);  in eliminateFrameIndex()
236         BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)  in eliminateFrameIndex()
250     if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {  in eliminateFrameIndex()
257     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);  in eliminateFrameIndex()
265       BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)  in eliminateFrameIndex()
276   auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MI.getOpcode());  in eliminateFrameIndex()
278     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);  in eliminateFrameIndex()
279     BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);  in eliminateFrameIndex()
282       BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)  in eliminateFrameIndex()
294   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;  in getFrameRegister()
322   if (RC == &RISCV::VMV0RegClass)  in getLargestLegalSuperClass()
323     return &RISCV::VRRegClass;  in getLargestLegalSuperClass()
337   unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);  in getOffsetOpcodes()