Lines Matching refs:RISCV
56 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
73 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
74 bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); } in isRV32E()
248 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { in RISCVAsmParser()
253 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { in RISCVAsmParser()
344 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
352 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum); in isGPR()
360 return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1); in isGPRPF64AsFPR()
998 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR16()
999 return Reg - RISCV::F0_D + RISCV::F0_H; in convertFPR64ToFPR16()
1003 assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); in convertFPR64ToFPR32()
1004 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32()
1011 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1013 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1015 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1018 return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, in convertVRToVRMx()
1030 RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); in validateTargetOperandClass()
1032 RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); in validateTargetOperandClass()
1033 bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg); in validateTargetOperandClass()
1299 assert(!(RegNo >= RISCV::F0_H && RegNo <= RISCV::F31_H)); in matchRegisterNameHelper()
1300 assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F)); in matchRegisterNameHelper()
1302 static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated"); in matchRegisterNameHelper()
1303 static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated"); in matchRegisterNameHelper()
1304 if (RegNo == RISCV::NoRegister) in matchRegisterNameHelper()
1306 if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31) in matchRegisterNameHelper()
1307 RegNo = RISCV::NoRegister; in matchRegisterNameHelper()
1308 return RegNo == RISCV::NoRegister; in matchRegisterNameHelper()
1362 if (RegNo == RISCV::NoRegister) { in parseRegister()
1799 if (RegNo == RISCV::NoRegister) in parseMaskReg()
1801 if (RegNo != RISCV::V0) in parseMaskReg()
1821 if (RegNo == RISCV::NoRegister) in parseGPRAsFPR()
1827 RegNo, S, E, isRV64(), !getSTI().hasFeature(RISCV::FeatureStdExtF))); in parseGPRAsFPR()
1965 if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) { in ParseInstruction()
2086 setFeatureBits(RISCV::FeatureStdExtC, "c"); in parseDirectiveOption()
2098 clearFeatureBits(RISCV::FeatureStdExtC, "c"); in parseDirectiveOption()
2134 setFeatureBits(RISCV::FeatureRelax, "relax"); in parseDirectiveOption()
2146 clearFeatureBits(RISCV::FeatureRelax, "relax"); in parseDirectiveOption()
2253 clearFeatureBits(RISCV::Feature64Bit, "64bit"); in parseDirectiveAttribute()
2255 setFeatureBits(RISCV::Feature64Bit, "64bit"); in parseDirectiveAttribute()
2310 MCRegister SrcReg = RISCV::X0; in emitLoadImm()
2320 RISCV::X0)); in emitLoadImm()
2354 Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi)); in emitAuipcInstPair()
2377 RISCV::ADDI, IDLoc, Out); in emitLoadLocalAddress()
2396 SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadAddress()
2399 SecondOpcode = RISCV::ADDI; in emitLoadAddress()
2415 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadTLSIEAddress()
2431 RISCV::ADDI, IDLoc, Out); in emitLoadTLSGDAddress()
2466 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
2471 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
2493 .addReg(RISCV::NoRegister)); in emitVMSGE()
2494 emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM) in emitVMSGE()
2503 assert(Inst.getOperand(0).getReg() != RISCV::V0 && in emitVMSGE()
2510 emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM) in emitVMSGE()
2513 .addReg(RISCV::V0)); in emitVMSGE()
2515 Inst.getOperand(0).getReg() == RISCV::V0) { in emitVMSGE()
2520 assert(Inst.getOperand(0).getReg() == RISCV::V0 && in emitVMSGE()
2522 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
2529 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
2539 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
2545 .addReg(RISCV::NoRegister)); in emitVMSGE()
2546 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
2548 .addReg(RISCV::V0) in emitVMSGE()
2550 emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM) in emitVMSGE()
2553 .addReg(RISCV::V0)); in emitVMSGE()
2554 emitToStreamer(Out, MCInstBuilder(RISCV::VMOR_MM) in emitVMSGE()
2563 assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction"); in checkPseudoAddTPRel()
2565 if (Inst.getOperand(2).getReg() != RISCV::X4) { in checkPseudoAddTPRel()
2575 return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(), in defaultMaskRegOp()
2581 if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T || in validateInstruction()
2582 Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) { in validateInstruction()
2612 if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { in validateInstruction()
2616 if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || in validateInstruction()
2617 Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || in validateInstruction()
2618 Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM || in validateInstruction()
2619 Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM || in validateInstruction()
2620 Opcode == RISCV::VMERGE_VXM) in validateInstruction()
2628 assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) && in validateInstruction()
2646 case RISCV::PseudoLI: { in processInstruction()
2652 emitToStreamer(Out, MCInstBuilder(RISCV::ADDI) in processInstruction()
2654 .addReg(RISCV::X0) in processInstruction()
2667 case RISCV::PseudoLLA: in processInstruction()
2670 case RISCV::PseudoLA: in processInstruction()
2673 case RISCV::PseudoLA_TLS_IE: in processInstruction()
2676 case RISCV::PseudoLA_TLS_GD: in processInstruction()
2679 case RISCV::PseudoLB: in processInstruction()
2680 emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2682 case RISCV::PseudoLBU: in processInstruction()
2683 emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2685 case RISCV::PseudoLH: in processInstruction()
2686 emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2688 case RISCV::PseudoLHU: in processInstruction()
2689 emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2691 case RISCV::PseudoLW: in processInstruction()
2692 emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2694 case RISCV::PseudoLWU: in processInstruction()
2695 emitLoadStoreSymbol(Inst, RISCV::LWU, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2697 case RISCV::PseudoLD: in processInstruction()
2698 emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false); in processInstruction()
2700 case RISCV::PseudoFLH: in processInstruction()
2701 emitLoadStoreSymbol(Inst, RISCV::FLH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2703 case RISCV::PseudoFLW: in processInstruction()
2704 emitLoadStoreSymbol(Inst, RISCV::FLW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2706 case RISCV::PseudoFLD: in processInstruction()
2707 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2709 case RISCV::PseudoSB: in processInstruction()
2710 emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2712 case RISCV::PseudoSH: in processInstruction()
2713 emitLoadStoreSymbol(Inst, RISCV::SH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2715 case RISCV::PseudoSW: in processInstruction()
2716 emitLoadStoreSymbol(Inst, RISCV::SW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2718 case RISCV::PseudoSD: in processInstruction()
2719 emitLoadStoreSymbol(Inst, RISCV::SD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2721 case RISCV::PseudoFSH: in processInstruction()
2722 emitLoadStoreSymbol(Inst, RISCV::FSH, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2724 case RISCV::PseudoFSW: in processInstruction()
2725 emitLoadStoreSymbol(Inst, RISCV::FSW, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2727 case RISCV::PseudoFSD: in processInstruction()
2728 emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
2730 case RISCV::PseudoAddTPRel: in processInstruction()
2734 case RISCV::PseudoSEXT_B: in processInstruction()
2737 case RISCV::PseudoSEXT_H: in processInstruction()
2740 case RISCV::PseudoZEXT_H: in processInstruction()
2743 case RISCV::PseudoZEXT_W: in processInstruction()
2746 case RISCV::PseudoVMSGEU_VX: in processInstruction()
2747 case RISCV::PseudoVMSGEU_VX_M: in processInstruction()
2748 case RISCV::PseudoVMSGEU_VX_M_T: in processInstruction()
2749 emitVMSGE(Inst, RISCV::VMSLTU_VX, IDLoc, Out); in processInstruction()
2751 case RISCV::PseudoVMSGE_VX: in processInstruction()
2752 case RISCV::PseudoVMSGE_VX_M: in processInstruction()
2753 case RISCV::PseudoVMSGE_VX_M_T: in processInstruction()
2754 emitVMSGE(Inst, RISCV::VMSLT_VX, IDLoc, Out); in processInstruction()
2756 case RISCV::PseudoVMSGE_VI: in processInstruction()
2757 case RISCV::PseudoVMSLT_VI: { in processInstruction()
2761 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI in processInstruction()
2762 : RISCV::VMSLE_VI; in processInstruction()
2770 case RISCV::PseudoVMSGEU_VI: in processInstruction()
2771 case RISCV::PseudoVMSLTU_VI: { in processInstruction()
2778 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI in processInstruction()
2779 ? RISCV::VMSEQ_VV in processInstruction()
2780 : RISCV::VMSNE_VV; in processInstruction()
2788 unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI in processInstruction()
2789 ? RISCV::VMSGTU_VI in processInstruction()
2790 : RISCV::VMSLEU_VI; in processInstruction()