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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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7bcfcabb |
| 28-Jun-2022 |
Alex Bradbury <[email protected]> |
[RISCV] Implement support for the Zicbop extension
Implements the ratified RISC-V Base Cache Management Operation ISA Extension: Zicbop, as described in https://github.com/riscv/riscv-CMOs/blob/mast
[RISCV] Implement support for the Zicbop extension
Implements the ratified RISC-V Base Cache Management Operation ISA Extension: Zicbop, as described in https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf.
This is implemented in a separate patch to Zicbom and Zicboz due to it requiring a new ASM operand type to be defined.
Differential Revision: https://reviews.llvm.org/D117433
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529f05cd |
| 24-Jun-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV][MC] Fold UIMM related code
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D128495
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Revision tags: llvmorg-14.0.6 |
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7a47ee51 |
| 21-Jun-2022 |
Kazu Hirata <[email protected]> |
[llvm] Don't use Optional::getValue (NFC)
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e0e687a6 |
| 20-Jun-2022 |
Kazu Hirata <[email protected]> |
[llvm] Don't use Optional::hasValue (NFC)
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Revision tags: llvmorg-14.0.5 |
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77e300ff |
| 05-Jun-2022 |
Fangrui Song <[email protected]> |
[MC] Change EndOfStatement "unexpected tokens in .xxx directive " to "expected newline"
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Revision tags: llvmorg-14.0.4 |
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d2ee2c9c |
| 24-May-2022 |
Craig Topper <[email protected]> |
[RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt.
Instead of matching opcodes to know the format to emit, use an enum value that we can get from the RISCVMatInt::Inst class.
[RISCV] Add an operand kind to the opcode/imm returned from RISCVMatInt.
Instead of matching opcodes to know the format to emit, use an enum value that we can get from the RISCVMatInt::Inst class.
Change the consumers to use fully covered switches so that we get a compiler warning if a new kind is added. With the opcode checks it was easier to forget to update one of the 3 consumers.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D126317
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2 |
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057c063c |
| 12-Apr-2022 |
Craig Topper <[email protected]> |
[RISCV] Add a encodeLMUL function to RISCVVType. NFC
This moves the encoding handling out of the assembly parser.
Reviewed By: khchen, frasercrmck
Differential Revision: https://reviews.llvm.org/D
[RISCV] Add a encodeLMUL function to RISCVVType. NFC
This moves the encoding handling out of the assembly parser.
Reviewed By: khchen, frasercrmck
Differential Revision: https://reviews.llvm.org/D123553
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Revision tags: llvmorg-14.0.1 |
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a276d1f4 |
| 31-Mar-2022 |
Fraser Cormack <[email protected]> |
[RISCV][NFC] Fix formatting on one line
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9a738c47 |
| 24-Mar-2022 |
Dávid Bolvanský <[email protected]> |
[NFCI] Fix set-but-unused warning in RISCVAsmParser.cpp
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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227496dc |
| 08-Mar-2022 |
luxufan <[email protected]> |
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
In the past, when construct RISCVAsmBackend, MCTargetOptions.ABIName would be passed and stored in RISCVAsmBackend. But MCT
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
In the past, when construct RISCVAsmBackend, MCTargetOptions.ABIName would be passed and stored in RISCVAsmBackend. But MCTargetOptions.ABIName can only be specified by -target-abi xxx in command line, if the .ll file has target-abi attribute, the codegen module will ignore it. And the generated object file would have incorrect EFlags value.
https://github.com/llvm/llvm-project/issues/50591 also caused by this problem.
This patch override the AsmPrinter::emitFunctionEntryLabel function and use it to set the target abi value that get from .ll file's target-abi attribute. And storing the target-abi in RISCVTargetStreamer instead of RISCVAsmBackend.
Differential Revision: https://reviews.llvm.org/D121183
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Revision tags: llvmorg-14.0.0-rc2 |
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0e38b295 |
| 01-Mar-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Rev
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D93298
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cf80ef13 |
| 17-Feb-2022 |
Eric Tang <[email protected]> |
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
Not only some AMO instructions but also other instructions need to process (${gpr}) or 0(${gpr}), where the 0 is be silently
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
Not only some AMO instructions but also other instructions need to process (${gpr}) or 0(${gpr}), where the 0 is be silently ignored.
This patch does some changes for general usage.
Signed-off-by: Eric Tang <[email protected]>
Differential Revision: https://reviews.llvm.org/D120017
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6aa8521f |
| 27-Feb-2022 |
Jessica Clarke <[email protected]> |
[RISCV] Fix parseBareSymbol to not double-parse top-level operators
By failing to lex the token we end up both parsing it as a binary operator ourselves and parsing it as a unary operator when calli
[RISCV] Fix parseBareSymbol to not double-parse top-level operators
By failing to lex the token we end up both parsing it as a binary operator ourselves and parsing it as a unary operator when calling parseExpression on the RHS. For plus this is harmless but for minus this parses "foo - 4" as "foo - -4", effectively treating a top-level minus as a plus.
Fixes https://github.com/llvm/llvm-project/issues/54105
Reviewed By: asb, MaskRay
Differential Revision: https://reviews.llvm.org/D120635
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c7fe6f9c |
| 24-Feb-2022 |
Nikita Popov <[email protected]> |
Revert "[RISCV] add the MC layer support of Zfinx extension"
This reverts commit 7798ecca9c3db42241169d31fea4fb820ed01830.
As reported in https://reviews.llvm.org/D93298#3331641 and following, this
Revert "[RISCV] add the MC layer support of Zfinx extension"
This reverts commit 7798ecca9c3db42241169d31fea4fb820ed01830.
As reported in https://reviews.llvm.org/D93298#3331641 and following, this causes assertion failures with inline assembly.
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7798ecca |
| 17-Feb-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Rev
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D93298
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06943537 |
| 09-Feb-2022 |
serge-sans-paille <[email protected]> |
Cleanup MCParser headers
As usual with that header cleanup series, some implicit dependencies now need to be explicit:
llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.
Cleanup MCParser headers
As usual with that header cleanup series, some implicit dependencies now need to be explicit:
llvm/MC/MCParser/MCAsmParser.h no longer includes llvm/MC/MCParser/MCAsmLexer.h
Preprocessed lines to build llvm on my setup: after: 1068185081 before: 1068324320
So no compile time benefit to expect, but we still get the looser coupling between files which is great.
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D119359
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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005fd8aa |
| 20-Jan-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV] Add support for Zihintpause extention
Add support for the 'pause' hint instruction as an alias for 'fence w, 0'. To do this allow the 'fence' operands pred and succ to be set to 0 (the empty
[RISCV] Add support for Zihintpause extention
Add support for the 'pause' hint instruction as an alias for 'fence w, 0'. To do this allow the 'fence' operands pred and succ to be set to 0 (the empty set). This will also allow future hints to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.
This patch revised from @mundaym's D93019.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D117789
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588f121a |
| 28-Jan-2022 |
Alex Bradbury <[email protected]> |
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
Where the instruction mnemonic contains a dot, we name the corresponding instruction in the .td fil
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
Where the instruction mnemonic contains a dot, we name the corresponding instruction in the .td file using a _ in the place of the dot. e.g. LR_W rather than LRW. This commit updates RISCVInstrInfoZb.td to follow that convention.
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e29d8fb1 |
| 24-Jan-2022 |
Wu Xinlong <[email protected]> |
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
This commit is currently implementing supports for scalar cryptography extension for LLVM according to version v1.0.0 of [
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
This commit is currently implementing supports for scalar cryptography extension for LLVM according to version v1.0.0 of [K Ext specification](https://github.com/riscv/riscv-crypto/releases)(scala crypto has been ratified already). Currently, we are implementing the MC (Machine Code) layer of his extension and the majority of work is done under `llvm/lib/Target/RISCV` directory. There are also some test files in `llvm/test/MC/RISCV` directory.
Remove the subfeature of Zbk* which conflict with b extensions to reduce the size of the patch. (Zbk* will be resubmit after this patch has been merged)
**Co-author:**@ksyx & @VincentWu & @lihongliang & @achieveartificialintelligence
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D98136
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a767ae2c |
| 19-Jan-2022 |
Luís Marques <[email protected]> |
[RISCV] Fix incomplete asm statement parsing
For instructions without operands, the final `AsmToken::EndOfStatement` wasn't being consumed. In the context of inline assembly, the resulting empty sta
[RISCV] Fix incomplete asm statement parsing
For instructions without operands, the final `AsmToken::EndOfStatement` wasn't being consumed. In the context of inline assembly, the resulting empty statements would cause extraneous empty lines to be emitted. Fix the issue by consuming the `EndOfStatement` token.
Differential Revision: https://reviews.llvm.org/D117565
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Revision tags: llvmorg-13.0.1-rc2 |
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f3a344d2 |
| 07-Jan-2022 |
Kazu Hirata <[email protected]> |
[Target] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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92153a9a |
| 07-Jan-2022 |
Liqin Weng <[email protected]> |
[RISCV] Support immediate vtype of VSETVLI/VSETIVLI in asm parser
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D115133
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e5947760 |
| 03-Jan-2022 |
Kazu Hirata <[email protected]> |
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base cl
Revert "[llvm] Remove redundant member initialization (NFC)"
This reverts commit fd4808887ee47f3ec8a030e9211169ef4fb094c3.
This patch causes gcc to issue a lot of warnings like:
warning: base class ‘class llvm::MCParsedAsmOperand’ should be explicitly initialized in the copy constructor [-Wextra]
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fd480888 |
| 02-Jan-2022 |
Kazu Hirata <[email protected]> |
[llvm] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
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10a71981 |
| 14-Dec-2021 |
Nelson Chu <[email protected]> |
[RISCV] Support named opcodes in .insn directive.
This patch is one of the TODO of commit, 283879793dc787225992496587581ec77b6b0610
We build the GenericTable for these opcodes, and also extend clas
[RISCV] Support named opcodes in .insn directive.
This patch is one of the TODO of commit, 283879793dc787225992496587581ec77b6b0610
We build the GenericTable for these opcodes, and also extend class RISCVOpcode, to store the names of opcodes. Then we call the parseInsnDirectiveOpcode to parse the opcode filed in .insn directive. We only allow users to write the recognized opcode names, or just write the immediate values in the 7 bits range.
Documentation: https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D115224
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