[RISCV][Clang] Add support for Zmmul extension

This patch implements recently ratified extension Zmmul, a subextension
of M (Integer Multiplication and Division) consisting only
multiplication part

[RISCV][Clang] Add support for Zmmul extension

This patch implements recently ratified extension Zmmul, a subextension
of M (Integer Multiplication and Division) consisting only
multiplication part of it.

Differential Revision: https://reviews.llvm.org/D103313
Reviewed By: craig.topper, jrtc27, asb

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[clang] Use value instead of getValue (NFC)

[clang] Don't use Optional::hasValue (NFC)

This patch replaces Optional::hasValue with the implicit cast to bool
in conditionals only.

Revert "Don't use Optional::hasValue (NFC)"

This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.

Don't use Optional::hasValue (NFC)

[clang] Use llvm::is_contained (NFC)

[RISCV] Recover the implication between Zve* extensions and the V extension.

This revision recover the implication between Zve* extensions and the V extension.

Differential Revision: https://review

[RISCV] Recover the implication between Zve* extensions and the V extension.

This revision recover the implication between Zve* extensions and the V extension.

Differential Revision: https://reviews.llvm.org/D119210

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[RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

Previously D113336 makes RISCVTargetInfo::initFeatureMap return the results
processed by RISCVISAInfo, which

[RISCV] Fix RISCVTargetInfo::initFeatureMap, add non-ISA features back after implication

Previously D113336 makes RISCVTargetInfo::initFeatureMap return the results
processed by RISCVISAInfo, which only consists of ISA features and misses
non-ISA features like `relax` and `save-restore`.

This patch fixes the problem.

Reviewed By: junparser

Differential Revision: https://reviews.llvm.org/D119541

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[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://

[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://reviews.llvm.org/D119250

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[RISCV] Decouple Zve* extensions and the V extension.

According to the spec, there are some difference between V and Zve64d. For example, the vmulh integer multiply variants that return the high wor

[RISCV] Decouple Zve* extensions and the V extension.

According to the spec, there are some difference between V and Zve64d. For example, the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*, but V extension does support these instructions. So we should decouple Zve* extensions and the V extension.

Differential Revision: https://reviews.llvm.org/D117854

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[RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. This mak

[RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

Under ASTContext, clang only copies the features from the options with
Target->initFeatureMap, and no implications is done there. This makes
clang_cc1 fail to imply into `zve32x` for the vector extension, and test
cases will have to add ` -target-feature +experimental-zve32x` in order
to work.

This patch fixes it.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D113336

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[RISCV] Add the zve extension according to the v1.0 spec

`zve` is the new standard vector extension to specify varying degrees of
vector support for embedding processors. The `zve` extension is rela

[RISCV] Add the zve extension according to the v1.0 spec

`zve` is the new standard vector extension to specify varying degrees of
vector support for embedding processors. The `zve` extension is related
to the `zvl` extension and other updates that are added in v1.0.

According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro `__riscv_v_max_elen`, `__riscv_v_max_elen_fp` for
`zve` and it can be used by applications that uses the vector extension.

Authored by: Zakk Chen <[email protected]> @khchen
Co-Authored by: Eop Chen <[email protected]> @eopXD

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D112408

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[RISCV] Add the zvl extension according to the v1.0 spec

`zvl` is the new standard vector extension that specifies the minimum vector length of the vector extension.
The `zvl` extension is related t

[RISCV] Add the zvl extension according to the v1.0 spec

`zvl` is the new standard vector extension that specifies the minimum vector length of the vector extension.
The `zvl` extension is related to the `zve` extension and other updates that are added in v1.0.

According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro `__riscv_v_min_vlen` for `zvl` and it can be used for applications that uses the vector extension.
LLVM checks whether the option `riscv-v-vector-bits-min` (if specified) matches the `zvl*` extension specified.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D108694

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[RISCV][Clang] Compute the default target-abi if it's empty.

Every generated IR has a corresponding target-abi value, so
encoding a non-empty value would improve the robustness and
correctness.

Rev

[RISCV][Clang] Compute the default target-abi if it's empty.

Every generated IR has a corresponding target-abi value, so
encoding a non-empty value would improve the robustness and
correctness.

Reviewed By: asb, jrtc27, arichardson

Differential Revision: https://reviews.llvm.org/D105555

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[RISCV] Split RISCV vector builtins into their own file and namespace.

Similar to SVE, this separates the RVV builtlins into their own
region of builtin IDs. Only those IDs are allowed to be used by

[RISCV] Split RISCV vector builtins into their own file and namespace.

Similar to SVE, this separates the RVV builtlins into their own
region of builtin IDs. Only those IDs are allowed to be used by
the builtin_alias attribute now.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D111923

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[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeat

[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::[email protected] for handling feature vector.
- RISCVTargetInfo::[email protected] for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to [email protected] or
[email protected] .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168

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[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tes

[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tests are updated or split accordingly.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D110669

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[RISCV] Remove experimental-b extension that includes all Zb* extensions

At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ra

[RISCV] Remove experimental-b extension that includes all Zb* extensions

At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ratified
together as a package. Unknown at this time when or if the other
Zb* extensions will be ratified.

This patch removes references to the B extension. I've updated and
split tests accordingly.

This has been split from D110669 to make review a little easier.

Differential Revision: https://reviews.llvm.org/D111338

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[RISCV] Remove Zbproposedc extension

This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't

[RISCV] Remove Zbproposedc extension

This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't think it makes sense to keep them in bitmanip. It
will eventually cause a conflict if/when Zce is implemented in llvm.

Differential Revision: https://reviews.llvm.org/D110871

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[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.

Differential Revision: https://reviews.llvm.org/D107139

[RISCV] Support machine constraint "S"

Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

extern int var;
void *addr_via_asm()

[RISCV] Support machine constraint "S"

Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

extern int var;
void *addr_via_asm() {
void *ret;
asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
return ret;
}

'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105254

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[RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this int

[RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.

The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this intrinsic
by just splitting the IR intrinsic since it works on individual bytes.

There will be other intrinsics in the future that would be harder
to support through splitting, for example grev, gorc, and shfl. Those
would require a compare and a select be inserted to check the MSB of
their control input.

This patch adds support for preventing this in the frontend with
a nice diagnostic.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D99984

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[RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'.

Add asm constraint 'vr' for vector registers.
Add asm constraint 'vm' for vector mask registers.

Differential Revision: http

[RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'.

Add asm constraint 'vr' for vector registers.
Add asm constraint 'vm' for vector mask registers.

Differential Revision: https://reviews.llvm.org/D98616

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[RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

Use that to print the diagnostic in SemaChecking instead of
listing all of the b

[RISCV] Make use of the required features in BuiltinInfo to store that V extension builtins require 'experimental-v'.

Use that to print the diagnostic in SemaChecking instead of
listing all of the builtins in a switch.

With the required features, IR generation will also be able
to error on this. Checking this here allows us to have a RISCV
focused error message.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D97826

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[RISCV] Add vadd with mask and without mask builtin.

Demonstrate how to add RISC-V V builtins and lower them to IR intrinsics for V extension.

Authored-by: Roger Ferrer Ibanez <[email protected]>

[RISCV] Add vadd with mask and without mask builtin.

Demonstrate how to add RISC-V V builtins and lower them to IR intrinsics for V extension.

Authored-by: Roger Ferrer Ibanez <[email protected]>
Co-Authored-by: Hsiangkai Wang <[email protected]>

Differential Revision: https://reviews.llvm.org/D93446

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