Lines Matching refs:RISCV
48 using namespace RISCV;
57 : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), in RISCVInstrInfo()
61 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) in getNop()
62 return MCInstBuilder(RISCV::C_NOP); in getNop()
63 return MCInstBuilder(RISCV::ADDI) in getNop()
64 .addReg(RISCV::X0) in getNop()
65 .addReg(RISCV::X0) in getNop()
74 case RISCV::LB: in isLoadFromStackSlot()
75 case RISCV::LBU: in isLoadFromStackSlot()
76 case RISCV::LH: in isLoadFromStackSlot()
77 case RISCV::LHU: in isLoadFromStackSlot()
78 case RISCV::FLH: in isLoadFromStackSlot()
79 case RISCV::LW: in isLoadFromStackSlot()
80 case RISCV::FLW: in isLoadFromStackSlot()
81 case RISCV::LWU: in isLoadFromStackSlot()
82 case RISCV::LD: in isLoadFromStackSlot()
83 case RISCV::FLD: in isLoadFromStackSlot()
101 case RISCV::SB: in isStoreToStackSlot()
102 case RISCV::SH: in isStoreToStackSlot()
103 case RISCV::SW: in isStoreToStackSlot()
104 case RISCV::FSH: in isStoreToStackSlot()
105 case RISCV::FSW: in isStoreToStackSlot()
106 case RISCV::SD: in isStoreToStackSlot()
107 case RISCV::FSD: in isStoreToStackSlot()
146 if (MBBI->getOpcode() == RISCV::PseudoVSETVLI || in isConvertibleToVMV_V_V()
147 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 || in isConvertibleToVMV_V_V()
148 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) { in isConvertibleToVMV_V_V()
168 if (MBBI->getOperand(0).getReg() != RISCV::X0) in isConvertibleToVMV_V_V()
172 if (MBBI->getOperand(1).getReg() != RISCV::X0) in isConvertibleToVMV_V_V()
201 if (MBBI->modifiesRegister(RISCV::VL)) in isConvertibleToVMV_V_V()
260 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
261 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
268 if (RISCV::VCSRRegClass.contains(SrcReg) && in copyPhysReg()
269 RISCV::GPRRegClass.contains(DstReg)) { in copyPhysReg()
271 BuildMI(MBB, MBBI, DL, get(RISCV::CSRRS), DstReg) in copyPhysReg()
273 .addReg(RISCV::X0); in copyPhysReg()
282 unsigned SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
283 if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
284 Opc = RISCV::FSGNJ_H; in copyPhysReg()
286 } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
287 Opc = RISCV::FSGNJ_S; in copyPhysReg()
289 } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
290 Opc = RISCV::FSGNJ_D; in copyPhysReg()
292 } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
293 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
295 } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
296 Opc = RISCV::PseudoVMV2R_V; in copyPhysReg()
298 } else if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
299 Opc = RISCV::PseudoVMV4R_V; in copyPhysReg()
301 } else if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
302 Opc = RISCV::PseudoVMV8R_V; in copyPhysReg()
304 } else if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
305 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
306 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
309 } else if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
310 Opc = RISCV::PseudoVMV2R_V; in copyPhysReg()
311 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
314 } else if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
315 Opc = RISCV::PseudoVMV4R_V; in copyPhysReg()
316 SubRegIdx = RISCV::sub_vrm4_0; in copyPhysReg()
319 } else if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
320 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
321 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
324 } else if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
325 Opc = RISCV::PseudoVMV2R_V; in copyPhysReg()
326 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
329 } else if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
330 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
331 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
334 } else if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
335 Opc = RISCV::PseudoVMV2R_V; in copyPhysReg()
336 SubRegIdx = RISCV::sub_vrm2_0; in copyPhysReg()
339 } else if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
340 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
341 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
344 } else if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
345 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
346 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
349 } else if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
350 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
351 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
354 } else if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
355 Opc = RISCV::PseudoVMV1R_V; in copyPhysReg()
356 SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg()
377 Opc = RISCV::PseudoVMV_V_V_M1; in copyPhysReg()
378 VIOpc = RISCV::PseudoVMV_V_I_M1; in copyPhysReg()
381 Opc = RISCV::PseudoVMV_V_V_M2; in copyPhysReg()
382 VIOpc = RISCV::PseudoVMV_V_I_M2; in copyPhysReg()
385 Opc = RISCV::PseudoVMV_V_V_M4; in copyPhysReg()
386 VIOpc = RISCV::PseudoVMV_V_I_M4; in copyPhysReg()
389 Opc = RISCV::PseudoVMV_V_V_M8; in copyPhysReg()
390 VIOpc = RISCV::PseudoVMV_V_I_M8; in copyPhysReg()
412 MIB.addReg(RISCV::VL, RegState::Implicit); in copyPhysReg()
413 MIB.addReg(RISCV::VTYPE, RegState::Implicit); in copyPhysReg()
442 MIB.addReg(RISCV::VL, RegState::Implicit); in copyPhysReg()
443 MIB.addReg(RISCV::VTYPE, RegState::Implicit); in copyPhysReg()
469 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
470 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in storeRegToStackSlot()
471 RISCV::SW : RISCV::SD; in storeRegToStackSlot()
473 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
474 Opcode = RISCV::FSH; in storeRegToStackSlot()
476 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
477 Opcode = RISCV::FSW; in storeRegToStackSlot()
479 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
480 Opcode = RISCV::FSD; in storeRegToStackSlot()
482 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
483 Opcode = RISCV::PseudoVSPILL_M1; in storeRegToStackSlot()
485 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
486 Opcode = RISCV::PseudoVSPILL_M2; in storeRegToStackSlot()
488 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
489 Opcode = RISCV::PseudoVSPILL_M4; in storeRegToStackSlot()
491 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
492 Opcode = RISCV::PseudoVSPILL_M8; in storeRegToStackSlot()
494 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
495 Opcode = RISCV::PseudoVSPILL2_M1; in storeRegToStackSlot()
496 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
497 Opcode = RISCV::PseudoVSPILL2_M2; in storeRegToStackSlot()
498 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
499 Opcode = RISCV::PseudoVSPILL2_M4; in storeRegToStackSlot()
500 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
501 Opcode = RISCV::PseudoVSPILL3_M1; in storeRegToStackSlot()
502 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
503 Opcode = RISCV::PseudoVSPILL3_M2; in storeRegToStackSlot()
504 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
505 Opcode = RISCV::PseudoVSPILL4_M1; in storeRegToStackSlot()
506 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
507 Opcode = RISCV::PseudoVSPILL4_M2; in storeRegToStackSlot()
508 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
509 Opcode = RISCV::PseudoVSPILL5_M1; in storeRegToStackSlot()
510 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
511 Opcode = RISCV::PseudoVSPILL6_M1; in storeRegToStackSlot()
512 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
513 Opcode = RISCV::PseudoVSPILL7_M1; in storeRegToStackSlot()
514 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
515 Opcode = RISCV::PseudoVSPILL8_M1; in storeRegToStackSlot()
533 MIB.addReg(RISCV::X0); in storeRegToStackSlot()
563 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
564 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in loadRegFromStackSlot()
565 RISCV::LW : RISCV::LD; in loadRegFromStackSlot()
567 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
568 Opcode = RISCV::FLH; in loadRegFromStackSlot()
570 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
571 Opcode = RISCV::FLW; in loadRegFromStackSlot()
573 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
574 Opcode = RISCV::FLD; in loadRegFromStackSlot()
576 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
577 Opcode = RISCV::PseudoVRELOAD_M1; in loadRegFromStackSlot()
579 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
580 Opcode = RISCV::PseudoVRELOAD_M2; in loadRegFromStackSlot()
582 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
583 Opcode = RISCV::PseudoVRELOAD_M4; in loadRegFromStackSlot()
585 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
586 Opcode = RISCV::PseudoVRELOAD_M8; in loadRegFromStackSlot()
588 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
589 Opcode = RISCV::PseudoVRELOAD2_M1; in loadRegFromStackSlot()
590 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
591 Opcode = RISCV::PseudoVRELOAD2_M2; in loadRegFromStackSlot()
592 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
593 Opcode = RISCV::PseudoVRELOAD2_M4; in loadRegFromStackSlot()
594 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
595 Opcode = RISCV::PseudoVRELOAD3_M1; in loadRegFromStackSlot()
596 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
597 Opcode = RISCV::PseudoVRELOAD3_M2; in loadRegFromStackSlot()
598 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
599 Opcode = RISCV::PseudoVRELOAD4_M1; in loadRegFromStackSlot()
600 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
601 Opcode = RISCV::PseudoVRELOAD4_M2; in loadRegFromStackSlot()
602 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
603 Opcode = RISCV::PseudoVRELOAD5_M1; in loadRegFromStackSlot()
604 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
605 Opcode = RISCV::PseudoVRELOAD6_M1; in loadRegFromStackSlot()
606 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
607 Opcode = RISCV::PseudoVRELOAD7_M1; in loadRegFromStackSlot()
608 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
609 Opcode = RISCV::PseudoVRELOAD8_M1; in loadRegFromStackSlot()
626 MIB.addReg(RISCV::X0); in loadRegFromStackSlot()
660 if (RISCV::isSEXT_W(MI)) { in foldMemoryOperandImpl()
661 LoadOpc = RISCV::LW; in foldMemoryOperandImpl()
664 if (RISCV::isZEXT_W(MI)) { in foldMemoryOperandImpl()
665 LoadOpc = RISCV::LWU; in foldMemoryOperandImpl()
668 if (RISCV::isZEXT_B(MI)) { in foldMemoryOperandImpl()
669 LoadOpc = RISCV::LBU; in foldMemoryOperandImpl()
673 case RISCV::SEXT_H: in foldMemoryOperandImpl()
674 LoadOpc = RISCV::LH; in foldMemoryOperandImpl()
676 case RISCV::SEXT_B: in foldMemoryOperandImpl()
677 LoadOpc = RISCV::LB; in foldMemoryOperandImpl()
679 case RISCV::ZEXT_H_RV32: in foldMemoryOperandImpl()
680 case RISCV::ZEXT_H_RV64: in foldMemoryOperandImpl()
681 LoadOpc = RISCV::LHU; in foldMemoryOperandImpl()
702 Register SrcReg = RISCV::X0; in movImm()
721 .addReg(RISCV::X0) in movImm()
747 case RISCV::BEQ: in getCondFromBranchOpc()
749 case RISCV::BNE: in getCondFromBranchOpc()
751 case RISCV::BLT: in getCondFromBranchOpc()
753 case RISCV::BGE: in getCondFromBranchOpc()
755 case RISCV::BLTU: in getCondFromBranchOpc()
757 case RISCV::BGEU: in getCondFromBranchOpc()
782 return get(RISCV::BEQ); in getBrCond()
784 return get(RISCV::BNE); in getBrCond()
786 return get(RISCV::BLT); in getBrCond()
788 return get(RISCV::BGE); in getBrCond()
790 return get(RISCV::BLTU); in getBrCond()
792 return get(RISCV::BGEU); in getBrCond()
930 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB); in insertBranch()
948 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB); in insertBranch()
974 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); in insertIndirectBranch()
977 MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump)) in insertIndirectBranch()
982 Register Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass, in insertIndirectBranch()
985 assert(Scav != RISCV::NoRegister && "No register is scavenged!"); in insertIndirectBranch()
1016 case RISCV::BEQ: in isBranchOffsetInRange()
1017 case RISCV::BNE: in isBranchOffsetInRange()
1018 case RISCV::BLT: in isBranchOffsetInRange()
1019 case RISCV::BGE: in isBranchOffsetInRange()
1020 case RISCV::BLTU: in isBranchOffsetInRange()
1021 case RISCV::BGEU: in isBranchOffsetInRange()
1023 case RISCV::JAL: in isBranchOffsetInRange()
1024 case RISCV::PseudoBR: in isBranchOffsetInRange()
1026 case RISCV::PseudoJump: in isBranchOffsetInRange()
1062 case RISCV::FSGNJ_D: in isAsCheapAsAMove()
1063 case RISCV::FSGNJ_S: in isAsCheapAsAMove()
1064 case RISCV::FSGNJ_H: in isAsCheapAsAMove()
1068 case RISCV::ADDI: in isAsCheapAsAMove()
1069 case RISCV::ORI: in isAsCheapAsAMove()
1070 case RISCV::XORI: in isAsCheapAsAMove()
1072 MI.getOperand(1).getReg() == RISCV::X0) || in isAsCheapAsAMove()
1085 case RISCV::ADDI: in isCopyInstrImpl()
1091 case RISCV::FSGNJ_D: in isCopyInstrImpl()
1092 case RISCV::FSGNJ_S: in isCopyInstrImpl()
1093 case RISCV::FSGNJ_H: in isCopyInstrImpl()
1280 return !C.isAvailableAcrossAndOutOfSeq(RISCV::X5, *TRI); in getOutliningCandidateInfo()
1304 .getFeatureBits()[RISCV::FeatureStdExtC]) in getOutliningCandidateInfo()
1348 if (MI.modifiesRegister(RISCV::X5, TRI) || in getOutliningType()
1349 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) in getOutliningType()
1384 MBB.addLiveIn(RISCV::X5); in buildOutlinedFrame()
1387 MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)) in buildOutlinedFrame()
1388 .addReg(RISCV::X0, RegState::Define) in buildOutlinedFrame()
1389 .addReg(RISCV::X5) in buildOutlinedFrame()
1399 BuildMI(MF, DebugLoc(), get(RISCV::PseudoCALLReg), RISCV::X5) in insertOutlinedCall()
1426 if ((MI.getOpcode() == RISCV::VSETVLI || MI.getOpcode() == RISCV::VSETIVLI || in createMIROperandComment()
1427 MI.getOpcode() == RISCV::PseudoVSETVLI || in createMIROperandComment()
1428 MI.getOpcode() == RISCV::PseudoVSETIVLI || in createMIROperandComment()
1429 MI.getOpcode() == RISCV::PseudoVSETVLIX0) && in createMIROperandComment()
1454 RISCV::PseudoV##OP##_##TYPE##_##LMUL
1595 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
1596 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
1728 RISCV::PseudoV##OP##_##LMUL##_TIED
1743 case RISCV::PseudoV##OP##_##LMUL##_TIED: \
1744 NewOpc = RISCV::PseudoV##OP##_##LMUL; \
1847 Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); in getVLENFactoredAmount()
1848 BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), VL) in getVLENFactoredAmount()
1856 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount()
1868 Opc = RISCV::SH3ADD; in getVLENFactoredAmount()
1871 Opc = RISCV::SH2ADD; in getVLENFactoredAmount()
1874 Opc = RISCV::SH1ADD; in getVLENFactoredAmount()
1880 BuildMI(MBB, II, DL, get(RISCV::SLLI), VL) in getVLENFactoredAmount()
1889 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); in getVLENFactoredAmount()
1891 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
1895 BuildMI(MBB, II, DL, get(RISCV::ADD), VL) in getVLENFactoredAmount()
1900 Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); in getVLENFactoredAmount()
1902 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in getVLENFactoredAmount()
1906 BuildMI(MBB, II, DL, get(RISCV::SUB), VL) in getVLENFactoredAmount()
1911 Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass); in getVLENFactoredAmount()
1918 BuildMI(MBB, II, DL, get(RISCV::MUL), VL) in getVLENFactoredAmount()
1928 bool RISCV::isSEXT_W(const MachineInstr &MI) { in isSEXT_W()
1929 return MI.getOpcode() == RISCV::ADDIW && MI.getOperand(1).isReg() && in isSEXT_W()
1934 bool RISCV::isZEXT_W(const MachineInstr &MI) { in isZEXT_W()
1935 return MI.getOpcode() == RISCV::ADD_UW && MI.getOperand(1).isReg() && in isZEXT_W()
1936 MI.getOperand(2).isReg() && MI.getOperand(2).getReg() == RISCV::X0; in isZEXT_W()
1940 bool RISCV::isZEXT_B(const MachineInstr &MI) { in isZEXT_B()
1941 return MI.getOpcode() == RISCV::ANDI && MI.getOperand(1).isReg() && in isZEXT_B()
1949 case RISCV::VS1R_V: in isRVVWholeLoadStore()
1950 case RISCV::VS2R_V: in isRVVWholeLoadStore()
1951 case RISCV::VS4R_V: in isRVVWholeLoadStore()
1952 case RISCV::VS8R_V: in isRVVWholeLoadStore()
1953 case RISCV::VL1RE8_V: in isRVVWholeLoadStore()
1954 case RISCV::VL2RE8_V: in isRVVWholeLoadStore()
1955 case RISCV::VL4RE8_V: in isRVVWholeLoadStore()
1956 case RISCV::VL8RE8_V: in isRVVWholeLoadStore()
1957 case RISCV::VL1RE16_V: in isRVVWholeLoadStore()
1958 case RISCV::VL2RE16_V: in isRVVWholeLoadStore()
1959 case RISCV::VL4RE16_V: in isRVVWholeLoadStore()
1960 case RISCV::VL8RE16_V: in isRVVWholeLoadStore()
1961 case RISCV::VL1RE32_V: in isRVVWholeLoadStore()
1962 case RISCV::VL2RE32_V: in isRVVWholeLoadStore()
1963 case RISCV::VL4RE32_V: in isRVVWholeLoadStore()
1964 case RISCV::VL8RE32_V: in isRVVWholeLoadStore()
1965 case RISCV::VL1RE64_V: in isRVVWholeLoadStore()
1966 case RISCV::VL2RE64_V: in isRVVWholeLoadStore()
1967 case RISCV::VL4RE64_V: in isRVVWholeLoadStore()
1968 case RISCV::VL8RE64_V: in isRVVWholeLoadStore()
1973 bool RISCV::isRVVSpill(const MachineInstr &MI) { in isRVVSpill()
1984 RISCV::isRVVSpillForZvlsseg(unsigned Opcode) { in isRVVSpillForZvlsseg()
1988 case RISCV::PseudoVSPILL2_M1: in isRVVSpillForZvlsseg()
1989 case RISCV::PseudoVRELOAD2_M1: in isRVVSpillForZvlsseg()
1991 case RISCV::PseudoVSPILL2_M2: in isRVVSpillForZvlsseg()
1992 case RISCV::PseudoVRELOAD2_M2: in isRVVSpillForZvlsseg()
1994 case RISCV::PseudoVSPILL2_M4: in isRVVSpillForZvlsseg()
1995 case RISCV::PseudoVRELOAD2_M4: in isRVVSpillForZvlsseg()
1997 case RISCV::PseudoVSPILL3_M1: in isRVVSpillForZvlsseg()
1998 case RISCV::PseudoVRELOAD3_M1: in isRVVSpillForZvlsseg()
2000 case RISCV::PseudoVSPILL3_M2: in isRVVSpillForZvlsseg()
2001 case RISCV::PseudoVRELOAD3_M2: in isRVVSpillForZvlsseg()
2003 case RISCV::PseudoVSPILL4_M1: in isRVVSpillForZvlsseg()
2004 case RISCV::PseudoVRELOAD4_M1: in isRVVSpillForZvlsseg()
2006 case RISCV::PseudoVSPILL4_M2: in isRVVSpillForZvlsseg()
2007 case RISCV::PseudoVRELOAD4_M2: in isRVVSpillForZvlsseg()
2009 case RISCV::PseudoVSPILL5_M1: in isRVVSpillForZvlsseg()
2010 case RISCV::PseudoVRELOAD5_M1: in isRVVSpillForZvlsseg()
2012 case RISCV::PseudoVSPILL6_M1: in isRVVSpillForZvlsseg()
2013 case RISCV::PseudoVRELOAD6_M1: in isRVVSpillForZvlsseg()
2015 case RISCV::PseudoVSPILL7_M1: in isRVVSpillForZvlsseg()
2016 case RISCV::PseudoVRELOAD7_M1: in isRVVSpillForZvlsseg()
2018 case RISCV::PseudoVSPILL8_M1: in isRVVSpillForZvlsseg()
2019 case RISCV::PseudoVRELOAD8_M1: in isRVVSpillForZvlsseg()
2024 bool RISCV::isFaultFirstLoad(const MachineInstr &MI) { in isFaultFirstLoad()
2025 return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) && in isFaultFirstLoad()