99   case RISCV::PseudoLLA:  in expandMI()
101   case RISCV::PseudoLA:  in expandMI()
103   case RISCV::PseudoLA_TLS_IE:  in expandMI()
105   case RISCV::PseudoLA_TLS_GD:  in expandMI()
107   case RISCV::PseudoVSETVLI:  in expandMI()
108   case RISCV::PseudoVSETVLIX0:  in expandMI()
109   case RISCV::PseudoVSETIVLI:  in expandMI()
111   case RISCV::PseudoVMCLR_M_B1:  in expandMI()
112   case RISCV::PseudoVMCLR_M_B2:  in expandMI()
113   case RISCV::PseudoVMCLR_M_B4:  in expandMI()
114   case RISCV::PseudoVMCLR_M_B8:  in expandMI()
115   case RISCV::PseudoVMCLR_M_B16:  in expandMI()
116   case RISCV::PseudoVMCLR_M_B32:  in expandMI()
117   case RISCV::PseudoVMCLR_M_B64:  in expandMI()
119     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);  in expandMI()
120   case RISCV::PseudoVMSET_M_B1:  in expandMI()
121   case RISCV::PseudoVMSET_M_B2:  in expandMI()
122   case RISCV::PseudoVMSET_M_B4:  in expandMI()
123   case RISCV::PseudoVMSET_M_B8:  in expandMI()
124   case RISCV::PseudoVMSET_M_B16:  in expandMI()
125   case RISCV::PseudoVMSET_M_B32:  in expandMI()
126   case RISCV::PseudoVMSET_M_B64:  in expandMI()
128     return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);  in expandMI()
129   case RISCV::PseudoVSPILL2_M1:  in expandMI()
130   case RISCV::PseudoVSPILL2_M2:  in expandMI()
131   case RISCV::PseudoVSPILL2_M4:  in expandMI()
132   case RISCV::PseudoVSPILL3_M1:  in expandMI()
133   case RISCV::PseudoVSPILL3_M2:  in expandMI()
134   case RISCV::PseudoVSPILL4_M1:  in expandMI()
135   case RISCV::PseudoVSPILL4_M2:  in expandMI()
136   case RISCV::PseudoVSPILL5_M1:  in expandMI()
137   case RISCV::PseudoVSPILL6_M1:  in expandMI()
138   case RISCV::PseudoVSPILL7_M1:  in expandMI()
139   case RISCV::PseudoVSPILL8_M1:  in expandMI()
141   case RISCV::PseudoVRELOAD2_M1:  in expandMI()
142   case RISCV::PseudoVRELOAD2_M2:  in expandMI()
143   case RISCV::PseudoVRELOAD2_M4:  in expandMI()
144   case RISCV::PseudoVRELOAD3_M1:  in expandMI()
145   case RISCV::PseudoVRELOAD3_M2:  in expandMI()
146   case RISCV::PseudoVRELOAD4_M1:  in expandMI()
147   case RISCV::PseudoVRELOAD4_M2:  in expandMI()
148   case RISCV::PseudoVRELOAD5_M1:  in expandMI()
149   case RISCV::PseudoVRELOAD6_M1:  in expandMI()
150   case RISCV::PseudoVRELOAD7_M1:  in expandMI()
151   case RISCV::PseudoVRELOAD8_M1:  in expandMI()
177   BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)  in expandAuipcInstPair()
203                              RISCV::ADDI);  in expandLoadLocalAddress()
215     SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;  in expandLoadAddress()
218     SecondOpcode = RISCV::ADDI;  in expandLoadAddress()
230   unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;  in expandLoadTLSIEAddress()
239                              RISCV::ADDI);  in expandLoadTLSGDAddress()
249   assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||  in expandVSetVL()
250           MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||  in expandVSetVL()
251           MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&  in expandVSetVL()
254   if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)  in expandVSetVL()
255     Opcode = RISCV::VSETIVLI;  in expandVSetVL()
257     Opcode = RISCV::VSETVLI;  in expandVSetVL()
293   auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());  in expandVSPILL()
299   unsigned Opcode = RISCV::VS1R_V;  in expandVSPILL()
300   unsigned SubRegIdx = RISCV::sub_vrm1_0;  in expandVSPILL()
301   static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,  in expandVSPILL()
304     Opcode = RISCV::VS2R_V;  in expandVSPILL()
305     SubRegIdx = RISCV::sub_vrm2_0;  in expandVSPILL()
306     static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,  in expandVSPILL()
309     Opcode = RISCV::VS4R_V;  in expandVSPILL()
310     SubRegIdx = RISCV::sub_vrm4_0;  in expandVSPILL()
311     static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,  in expandVSPILL()
327       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)  in expandVSPILL()
343   auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(MBBI->getOpcode());  in expandVRELOAD()
349   unsigned Opcode = RISCV::VL1RE8_V;  in expandVRELOAD()
350   unsigned SubRegIdx = RISCV::sub_vrm1_0;  in expandVRELOAD()
351   static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7,  in expandVRELOAD()
354     Opcode = RISCV::VL2RE8_V;  in expandVRELOAD()
355     SubRegIdx = RISCV::sub_vrm2_0;  in expandVRELOAD()
356     static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3,  in expandVRELOAD()
359     Opcode = RISCV::VL4RE8_V;  in expandVRELOAD()
360     SubRegIdx = RISCV::sub_vrm4_0;  in expandVRELOAD()
361     static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1,  in expandVRELOAD()
372       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)  in expandVRELOAD()