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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4 |
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c644488a |
| 15-May-2022 |
Sheng <[email protected]> |
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
The name `MCFixedLenDisassembler.h` is out of date after D120958.
Rename it as `MCDecoderOps.h` to reflect the change.
Reviewed By: myhsu
Dif
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
The name `MCFixedLenDisassembler.h` is out of date after D120958.
Rename it as `MCDecoderOps.h` to reflect the change.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D124987
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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4ae9745a |
| 21-Mar-2022 |
Maksim Panchenko <[email protected]> |
[Disassember][NFCI] Use strong type for instruction decoder
All LLVM backends use MCDisassembler as a base class for their instruction decoders. Use "const MCDisassembler *" for the decoder instead
[Disassember][NFCI] Use strong type for instruction decoder
All LLVM backends use MCDisassembler as a base class for their instruction decoders. Use "const MCDisassembler *" for the decoder instead of "const void *". Remove unnecessary static casts.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D122245
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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0e38b295 |
| 01-Mar-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Rev
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D93298
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c7fe6f9c |
| 24-Feb-2022 |
Nikita Popov <[email protected]> |
Revert "[RISCV] add the MC layer support of Zfinx extension"
This reverts commit 7798ecca9c3db42241169d31fea4fb820ed01830.
As reported in https://reviews.llvm.org/D93298#3331641 and following, this
Revert "[RISCV] add the MC layer support of Zfinx extension"
This reverts commit 7798ecca9c3db42241169d31fea4fb820ed01830.
As reported in https://reviews.llvm.org/D93298#3331641 and following, this causes assertion failures with inline assembly.
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7798ecca |
| 17-Feb-2022 |
Shao-Ce SUN <[email protected]> |
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Rev
[RISCV] add the MC layer support of Zfinx extension
This patch added the MC layer support of Zfinx extension.
Authored-by: StephenFan Co-Authored-by: Shao-Ce Sun
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D93298
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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89b57061 |
| 08-Oct-2021 |
Reid Kleckner <[email protected]> |
Move TargetRegistry.(h|cpp) from Support to MC
This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually us
Move TargetRegistry.(h|cpp) from Support to MC
This moves the registry higher in the LLVM library dependency stack. Every client of the target registry needs to link against MC anyway to actually use the target, so we might as well move this out of Support.
This allows us to ensure that Support doesn't have includes from MC/*.
Differential Revision: https://reviews.llvm.org/D111454
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a21c5579 |
| 30-Sep-2021 |
Craig Topper <[email protected]> |
[RISCV] Remove Zbproposedc extension
This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w. I believe these have been picked up by the Zce effort using different encodings. I don't
[RISCV] Remove Zbproposedc extension
This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w. I believe these have been picked up by the Zce effort using different encodings. I don't think it makes sense to keep them in bitmanip. It will eventually cause a conflict if/when Zce is implemented in llvm.
Differential Revision: https://reviews.llvm.org/D110871
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3 |
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f2933610 |
| 13-Sep-2021 |
Jim Lin <[email protected]> |
[RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension
Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension for consistency
Reviewed By: HsiangKai, asb
Diff
[RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension
Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension for consistency
Reviewed By: HsiangKai, asb
Differential Revision: https://reviews.llvm.org/D108187
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Revision tags: llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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a2d19bad |
| 09-Feb-2021 |
Hsiangkai Wang <[email protected]> |
[RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store instructions. I suggest to use the whole register load/store instructions fo
[RISCV] Use whole register load/store for generic load/store.
In vector v0.10, there are whole vector register load/store instructions. I suggest to use the whole register load/store instructions for generic load/store for scalable vector types. It could save up vset{i}vl{i} for these load/store.
For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to load/store partial vector registers.
Differential Revision: https://reviews.llvm.org/D95853
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2 |
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387d3c24 |
| 14-Jan-2021 |
Craig Topper <[email protected]> |
[RISCV] Merge Utils library into MCTargetDesc
MCTargetDesc includes headers from Utils and Utils includes headers from MCTargetDesc. So from a library layering perspective it makes sense for them to
[RISCV] Merge Utils library into MCTargetDesc
MCTargetDesc includes headers from Utils and Utils includes headers from MCTargetDesc. So from a library layering perspective it makes sense for them to be in the same library. I guess the other option might be to move the tablegen includes from RISCVMCTargetDesc.h to RISCVBaseInfo.h so that RISCVBaseInfo.h didn't need to include RISCVMCTargetDesc.h. Everything else that depends on Utils also depends on MCTargetDesc so having one library seemed simpler.
Differential Revision: https://reviews.llvm.org/D93168
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Revision tags: llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3 |
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f7bc7c29 |
| 03-Jul-2020 |
Hsiangkai Wang <[email protected]> |
[RISCV] Support Zfh half-precision floating-point extension.
Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex
Differential Revision: https://revie
[RISCV] Support Zfh half-precision floating-point extension.
Support "Zfh" extension according to https://github.com/riscv/riscv-isa-manual/blob/zfh/src/zfh.tex
Differential Revision: https://reviews.llvm.org/D90738
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0add5f91 |
| 12-Nov-2020 |
Craig Topper <[email protected]> |
[RISCV] Don't include CodeGen layer files in MC layer
-Use MCRegister instead of Register in MC layer. -Move some enums from RISCVInstrInfo.h to RISCVBaseInfo.h to be with other TSFlags bits.
Diffe
[RISCV] Don't include CodeGen layer files in MC layer
-Use MCRegister instead of Register in MC layer. -Move some enums from RISCVInstrInfo.h to RISCVBaseInfo.h to be with other TSFlags bits.
Differential Revision: https://reviews.llvm.org/D91114
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Revision tags: llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1 |
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66da87dc |
| 24-Oct-2019 |
Hsiangkai Wang <[email protected]> |
[RISCV] Assemble/Disassemble v-ext instructions.
Assemble/disassemble RISC-V V extension instructions according to latest version spec in https://github.com/riscv/riscv-v-spec/.
I have tested this
[RISCV] Assemble/Disassemble v-ext instructions.
Assemble/disassemble RISC-V V extension instructions according to latest version spec in https://github.com/riscv/riscv-v-spec/.
I have tested this patch using GNU toolchain. The encoding is aligned to GNU assembler output. In this patch, there is a test case for each instruction at least.
The V register definition is just for assemble/disassemble. Its type is not important in this stage. I think it will be reviewed and modified as we want to do codegen for scalable vector types.
This patch does not include Zvamo, Zvlsseg, and Zvediv.
Differential revision: https://reviews.llvm.org/D69987
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fae40bd5 |
| 09-Apr-2020 |
Paolo Savini <[email protected]> |
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92)
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status.
Differential Revision: https://reviews.llvm.org/D65649
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0dbcb363 |
| 15-Jan-2020 |
Tom Stellard <[email protected]> |
CMake: Make most target symbols hidden by default
Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF this change makes all symbols in the target specific libraries hidden by
CMake: Make most target symbols hidden by default
Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF this change makes all symbols in the target specific libraries hidden by default.
A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark symbols in these libraries public, which is mainly needed for the definitions of the LLVMInitialize* functions.
This patch reduces the number of public symbols in libLLVM.so by about 25%. This should improve load times for the dynamic library and also make abi checker tools, like abidiff require less memory when analyzing libLLVM.so
One side-effect of this change is that for builds with LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that access symbols that are no longer public will need to be statically linked.
Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1): nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 36221 nm after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 26278
Reviewers: chandlerc, beanz, mgorny, rnk, hans
Reviewed By: rnk, hans
Subscribers: merge_guards_bot, luismarques, smeenai, ldionne, lenary, s.egerton, pzheng, sameer.abuasal, MaskRay, wuzish, echristo, Jim, hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, kristina, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54439
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6fdd6a7b |
| 11-Jan-2020 |
Fangrui Song <[email protected]> |
[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()
The argument is llvm::null() everywhere except llvm::errs() in llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It
[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()
The argument is llvm::null() everywhere except llvm::errs() in llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds.
If we ever have the needs to add verbose log to disassemblers, we can record log with a member function, instead of passing it around as an argument.
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aae97bfd |
| 27-Sep-2019 |
Luis Marques <[email protected]> |
[RISCV] Rename FPRs and use Register arithmetic
The new names for FPRs ensure that the Register values within the same class are enumerated consecutively (the order is determined by the `LessRecordR
[RISCV] Rename FPRs and use Register arithmetic
The new names for FPRs ensure that the Register values within the same class are enumerated consecutively (the order is determined by the `LessRecordRegister` function object). Where there were tables mapping between 32- and 64-bit FPRs (and vice versa) this patch replaces them with Register arithmetic. The enumeration order between different register classes is expected to continue to be arbitrary, although it does impact the conversion from the (overloaded) asm FPR names to Register values, and therefore might require updates to the target if the sorting algorithm is changed. Static asserts were added to ensure that changes to the ordering that would impact the current implementation are detected.
Differential Revision: https://reviews.llvm.org/D67423
llvm-svn: 373096
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Revision tags: llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3 |
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f7cdff4f |
| 21-Aug-2019 |
Luis Marques <[email protected]> |
[RISCV] Remove fix introduced by r369573, superseded by r369580
llvm-svn: 369590
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4f488b59 |
| 21-Aug-2019 |
Luis Marques <[email protected]> |
[RISCV] Fix use of side-effects in asserts in decoder functions
llvm-svn: 369580
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b73cd336 |
| 21-Aug-2019 |
Richard Smith <[email protected]> |
Fix -Werror=unused-variable error after r369528.
llvm-svn: 369573
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c3bf3d14 |
| 21-Aug-2019 |
Luis Marques <[email protected]> |
[RISCV] Add support for RVC HINT instructions
The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints.
Differential Revision:
[RISCV] Add support for RVC HINT instructions
The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints.
Differential Revision: https://reviews.llvm.org/D62592
llvm-svn: 369528
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fa06e958 |
| 16-Aug-2019 |
Luis Marques <[email protected]> |
[RISCV] Convert registers from unsigned to Register
Only in public interfaces that have not yet been converted should there remain registers with unsigned type.
Differential Revision: https://revie
[RISCV] Convert registers from unsigned to Register
Only in public interfaces that have not yet been converted should there remain registers with unsigned type.
Differential Revision: https://reviews.llvm.org/D66252
llvm-svn: 369114
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Revision tags: llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2 |
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4b0b2619 |
| 11-Jun-2019 |
Tom Stellard <[email protected]> |
Revert CMake: Make most target symbols hidden by default
This reverts r362990 (git commit 374571301dc8e9bc9fdd1d70f86015de198673bd)
This was causing linker warnings on Darwin:
ld: warning: direct
Revert CMake: Make most target symbols hidden by default
This reverts r362990 (git commit 374571301dc8e9bc9fdd1d70f86015de198673bd)
This was causing linker warnings on Darwin:
ld: warning: direct access in function 'llvm::initializeEvexToVexInstPassPass(llvm::PassRegistry&)' from file '../../lib/libLLVMX86CodeGen.a(X86EvexToVex.cpp.o)' to global weak symbol 'void std::__1::__call_once_proxy<std::__1::tuple<void* (&)(llvm::PassRegistry&), std::__1::reference_wrapper<llvm::PassRegistry>&&> >(void*)' from file '../../lib/libLLVMCore.a(Verifier.cpp.o)' means the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with different visibility settings.
llvm-svn: 363028
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| #
37457130 |
| 10-Jun-2019 |
Tom Stellard <[email protected]> |
CMake: Make most target symbols hidden by default
Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF this change makes all symbols in the target specific libraries hidden by
CMake: Make most target symbols hidden by default
Summary: For builds with LLVM_BUILD_LLVM_DYLIB=ON and BUILD_SHARED_LIBS=OFF this change makes all symbols in the target specific libraries hidden by default.
A new macro called LLVM_EXTERNAL_VISIBILITY has been added to mark symbols in these libraries public, which is mainly needed for the definitions of the LLVMInitialize* functions.
This patch reduces the number of public symbols in libLLVM.so by about 25%. This should improve load times for the dynamic library and also make abi checker tools, like abidiff require less memory when analyzing libLLVM.so
One side-effect of this change is that for builds with LLVM_BUILD_LLVM_DYLIB=ON and LLVM_LINK_LLVM_DYLIB=ON some unittests that access symbols that are no longer public will need to be statically linked.
Before and after public symbol counts (using gcc 8.2.1, ld.bfd 2.31.1): nm before/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 36221 nm after/libLLVM-9svn.so | grep ' [A-Zuvw] ' | wc -l 26278
Reviewers: chandlerc, beanz, mgorny, rnk, hans
Reviewed By: rnk, hans
Subscribers: Jim, hiraditya, michaelplatings, chapuni, jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, kristina, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D54439
llvm-svn: 362990
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Revision tags: llvmorg-8.0.1-rc1 |
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| #
51fc56d6 |
| 15-May-2019 |
Richard Trieu <[email protected]> |
[RISCV] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes
[RISCV] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem.
llvm-svn: 360732
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