66   bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];  in DecodeGPRRegisterClass()
71   MCRegister Reg = RISCV::X0 + RegNo;  in DecodeGPRRegisterClass()
82   MCRegister Reg = RISCV::F0_H + RegNo;  in DecodeFPR16RegisterClass()
93   MCRegister Reg = RISCV::F0_F + RegNo;  in DecodeFPR32RegisterClass()
104   MCRegister Reg = RISCV::F8_F + RegNo;  in DecodeFPR32CRegisterClass()
115   MCRegister Reg = RISCV::F0_D + RegNo;  in DecodeFPR64RegisterClass()
126   MCRegister Reg = RISCV::F8_D + RegNo;  in DecodeFPR64CRegisterClass()
157   MCRegister Reg = RISCV::X8 + RegNo;  in DecodeGPRCRegisterClass()
168   MCRegister Reg = RISCV::X0 + RegNo;  in DecodeGPRPF64RegisterClass()
179   MCRegister Reg = RISCV::V0 + RegNo;  in DecodeVRRegisterClass()
197       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,  in DecodeVRM2RegisterClass()
198                               &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);  in DecodeVRM2RegisterClass()
217       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,  in DecodeVRM4RegisterClass()
218                               &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);  in DecodeVRM4RegisterClass()
237       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,  in DecodeVRM8RegisterClass()
238                               &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);  in DecodeVRM8RegisterClass()
247   MCRegister Reg = RISCV::NoRegister;  in decodeVMaskReg()
252     Reg = RISCV::V0;  in decodeVMaskReg()
265   if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||  in addImplySP()
266       Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||  in addImplySP()
267       Inst.getOpcode() == RISCV::C_FLWSP ||  in addImplySP()
268       Inst.getOpcode() == RISCV::C_FSWSP ||  in addImplySP()
269       Inst.getOpcode() == RISCV::C_FLDSP ||  in addImplySP()
270       Inst.getOpcode() == RISCV::C_FSDSP ||  in addImplySP()
271       Inst.getOpcode() == RISCV::C_ADDI4SPN) {  in addImplySP()
274   if (Inst.getOpcode() == RISCV::C_ADDI16SP) {  in addImplySP()
447     if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&  in getInstruction()
448         !STI.getFeatureBits()[RISCV::Feature64Bit]) {  in getInstruction()
459     if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {  in getInstruction()
478     if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {  in getInstruction()