[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`

Fix build errors in D126794

```
ld.lld: error: undefined symbol: llvm::MachineInstr::getNumExplicitDefs() const
>>> referenced by RISCVBaseInfo

[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`

Fix build errors in D126794

```
ld.lld: error: undefined symbol: llvm::MachineInstr::getNumExplicitDefs() const
>>> referenced by RISCVBaseInfo.cpp
>>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a

ld.lld: error: undefined symbol: llvm::MachineInstr::findRegisterDefOperandIdx(llvm::Register, bool, bool, llvm::TargetRegisterInfo const*) const
>>> referenced by RISCVBaseInfo.cpp
>>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a
clang-15: error: linker command failed with exit code 1 (use -v to see invocation)
```

Reviewed By: fakepaper56, craig.topper

Differential Revision: https://reviews.llvm.org/D127477

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Revert "[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`"

This reverts commit e018e493c1ac514504bbaa1d1396aec025142a31.

There are some problems with this commit,
related revision: https://revi

Revert "[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`"

This reverts commit e018e493c1ac514504bbaa1d1396aec025142a31.

There are some problems with this commit,
related revision: https://reviews.llvm.org/D127477

show more ...

[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`

Fix build errors in D126794

```
ld.lld: error: undefined symbol: llvm::MachineInstr::getNumExplicitDefs() const
>>> referenced by RISCVBaseInfo

[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`

Fix build errors in D126794

```
ld.lld: error: undefined symbol: llvm::MachineInstr::getNumExplicitDefs() const
>>> referenced by RISCVBaseInfo.cpp
>>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a

ld.lld: error: undefined symbol: llvm::MachineInstr::findRegisterDefOperandIdx(llvm::Register, bool, bool, llvm::TargetRegisterInfo const*) const
>>> referenced by RISCVBaseInfo.cpp
>>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a
clang-15: error: linker command failed with exit code 1 (use -v to see invocation)
```

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D127477

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[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

The patch is a replacement of D125199. PseudoReadVL with vtype has worry for
computing same vtypes of VLEFF/VLSEGFF in two diffe

[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

The patch is a replacement of D125199. PseudoReadVL with vtype has worry for
computing same vtypes of VLEFF/VLSEGFF in two different places, DAGToDAG and
InsertVSETVLI. VLEFF/VLSEGFF MI with VL output still could provide the vtype of
VLEFF/VLSEGFF to the users of its VL.

The patch names the new pseudo as original VLEFF/VLSEGFF name suffixed "_VL" and
expand them in RISCVInsertVSETVLI pass.

This patch also reverts commit 4537aae0d57e17c217c192d8977012ba475b130c,
"[RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.".

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126794

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[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D120899

[RISCV] Update computeTargetABI from llc as well as clang

Clang computes the default ABI if -mabi is empty
and encode it in LLVM IR module flag since D105555.
For correctness, llc need to give the s

[RISCV] Update computeTargetABI from llc as well as clang

Clang computes the default ABI if -mabi is empty
and encode it in LLVM IR module flag since D105555.
For correctness, llc need to give the same target-abi
(Options.MCOptions.ABIName) with ABI encoded in IR.
The getSubtargetImpl already has a check for them only if
Options.MCOptions.ABIName is not empty.

In order to get more robustness we could have a check for
explicit ABI, but now we have two different logic to
compute the default ABI.

The front-end ABI is defautl to the ilp32/ilp32e/lp64, and
ilp32d/lp64d when hardware support for extension D.
The backend ABI is default to the ilp32/ilp32e/lp64.

Reviewed by: asb, jrtc27

Differential Revision: https://reviews.llvm.org/D118333

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[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://

[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://reviews.llvm.org/D119250

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[RISCV] Support named opcodes in .insn directive.

This patch is one of the TODO of commit, 283879793dc787225992496587581ec77b6b0610

We build the GenericTable for these opcodes, and also extend clas

[RISCV] Support named opcodes in .insn directive.

This patch is one of the TODO of commit, 283879793dc787225992496587581ec77b6b0610

We build the GenericTable for these opcodes, and also extend class RISCVOpcode, to store the names of opcodes. Then we call the parseInsnDirectiveOpcode to parse the opcode filed in .insn directive. We only allow users to write the recognized opcode names, or just write the immediate values in the 7 bits range.

Documentation: https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D115224

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[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeat

[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::[email protected] for handling feature vector.
- RISCVTargetInfo::[email protected] for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to [email protected] or
[email protected] .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168

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[RISCV][NFC] Add a single space after comma for VType

In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llv

[RISCV][NFC] Add a single space after comma for VType

In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790

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Fix "not all control paths return a value" MSVC warning. NFCI.

[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0

[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.

There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103215

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[RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

The VSEW encoding isn't a useful value to pass around. It's better
to use SEW or log2(SEW) directly. The only real ugliness

[RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

The VSEW encoding isn't a useful value to pass around. It's better
to use SEW or log2(SEW) directly. The only real ugliness is that
the vsetvli IR intrinsics use the VSEW encoding, but it's easy
enough to decode that when the intrinsic is processed.

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[RISCV] Move instruction information into the RISCVII namespace (NFC)

Move instruction attributes into the `RISCVII` namespace and add associated helper functions.

Differential Revision: https://re

[RISCV] Move instruction information into the RISCVII namespace (NFC)

Move instruction attributes into the `RISCVII` namespace and add associated helper functions.

Differential Revision: https://reviews.llvm.org/D102268

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[RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple.

I encountered a project that uses llvm that passes "

[RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple.

I encountered a project that uses llvm that passes "generic" by
default. While I could fix that project, I wouldn't be surprised
if other projects did something similar. So it seems like
a good idea to provide a better error here.

I've also added validation of the 64Bit feature against the
triple so that we can catch a mismatched CPU before failing in
a mysterious way. We can make it pretty far in isel because we
calculate XLenVT from the triple and use that to set up the legal
integer type.

Reviewed By: luismarques, khchen

Differential Revision: https://reviews.llvm.org/D98307

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[RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC

RISCVBaseInfo.h belongs to the MC layer, but the Pseudo instructions
are only used by the CodeGen layer. So it makes sen

[RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC

RISCVBaseInfo.h belongs to the MC layer, but the Pseudo instructions
are only used by the CodeGen layer. So it makes sense to keep this
table in the CodeGen layer.

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[RISCV] Merge Utils library into MCTargetDesc

MCTargetDesc includes headers from Utils and Utils includes headers
from MCTargetDesc. So from a library layering perspective it makes sense
for them to

[RISCV] Merge Utils library into MCTargetDesc

MCTargetDesc includes headers from Utils and Utils includes headers
from MCTargetDesc. So from a library layering perspective it makes sense
for them to be in the same library. I guess the other option might be to
move the tablegen includes from RISCVMCTargetDesc.h to RISCVBaseInfo.h
so that RISCVBaseInfo.h didn't need to include RISCVMCTargetDesc.h.
Everything else that depends on Utils also depends on MCTargetDesc so
having one library seemed simpler.

Differential Revision: https://reviews.llvm.org/D93168

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