[RISCV] Recognize bexti from (srl (and X, 1<<C), C).

This is the form we get for (zext (setne (and X 1<<C))). We only
had bexti patterns for the alternative form (and (srl X, C), 1).

[RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel.

Prefer to use SLLI instead of zext.w/zext.h in more cases. SLLI
might be better for compression.

[RISCV] Remove doPeepholeLoadStoreADDI.

All of the cases should be handled by SelectAddrRegImm now.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D129451

[RISCV] Move the custom isel for (add X, imm) into SelectAddrRegImm.

This custom isel was used to split the lo12 bits of the imm so that
they could be folded into load/store addresses via a post-ise

[RISCV] Move the custom isel for (add X, imm) into SelectAddrRegImm.

This custom isel was used to split the lo12 bits of the imm so that
they could be folded into load/store addresses via a post-isel
peephole.

This patch instead splits the immediate during isel and folds the
lo12 removing the need for the post-isel peephole to do anything.

After this we'll be able to remove the post-isel peephole.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D129450

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[RISCV] Modify the custom isel for (add X, imm) used by load/stores.

We have custom isel that tries to select the Lo12 bits using a
separate ADDI that can later folded into the load/store address
by

[RISCV] Modify the custom isel for (add X, imm) used by load/stores.

We have custom isel that tries to select the Lo12 bits using a
separate ADDI that can later folded into the load/store address
by the post-isel peephole.

This patch disables this if the load/store already had a non-zero
offset. A non-zero offset implies that CodeGenPrepare split several
large offsets used by different loads and stores into a common large
offset and multiple small offsets that could be folded. Folding more
of the lo12 bits changes this common offset by increasing the small
offsets. While this can save an instruction to materialize the common
offset, it can also prevent the small offsets from fitting in a
compressed load/store instruction.

Removing this also simplifies the last piece needed to fold the custom
isel for add into SelectAddrRegImm and remove the post-isel peephole.

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[RISCV] Support folding constant addresses in SelectAddrRegImm.

We already handled this by folding an ADDI in the post-isel peephole.
My goal is to remove that peephole so this adds the functionalit

[RISCV] Support folding constant addresses in SelectAddrRegImm.

We already handled this by folding an ADDI in the post-isel peephole.
My goal is to remove that peephole so this adds the functionality
to isel.

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[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)

It might be possible to rewrite (and (shl/shr X, C2), C1) in a way
that gives us a left shift that can be folded into a

[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)

It might be possible to rewrite (and (shl/shr X, C2), C1) in a way
that gives us a left shift that can be folded into a SHXADD.

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[RISCV] Use a switch statement in PreprocessISelDAG. NFC

This should make it easier to add more peepholes in the future.

[RISCV] Update PreprocessISelDAG to use RemoveDeadNodes.

Instead of deleting nodes as we go, delete all dead nodes if a
change is made. This allows adding peepholes that might make
multiple nodes de

[RISCV] Update PreprocessISelDAG to use RemoveDeadNodes.

Instead of deleting nodes as we go, delete all dead nodes if a
change is made. This allows adding peepholes that might make
multiple nodes dead.

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[RISCV] Replace an explicit check with an assert.

Shift amounts should never be 0 or more than bitwidth - 1.

[RISCV] Rename some variables for clarity. NFC

[RISCV] Add ADDI instr for computing FrameIndex address

RVV doesn't have immediate field for memory addressing. Currently
we build MachineInstructions in PEI to computing stack offset for
RVV load s

[RISCV] Add ADDI instr for computing FrameIndex address

RVV doesn't have immediate field for memory addressing. Currently
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.

This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as `ADDI GPR, targetframeindex`.

There are 2 advantages for such change:
1. Stack objects address computing can be optimized by machine function
passes.
2. Since the ADDI instruction's destination register can be used as a
temp register, we can save an emergency spill slot.

Differential Revision: https://reviews.llvm.org/D128187

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[RISCV] Add more SHXADD patterns.

This handles the code we get for this.

int foo(unsigned x, int *y) {
return y[x >> 3];
}

The srl and shl implied by the array index will be combined to
form (

[RISCV] Add more SHXADD patterns.

This handles the code we get for this.

int foo(unsigned x, int *y) {
return y[x >> 3];
}

The srl and shl implied by the array index will be combined to
form (srl (and X, C2), C1). We need to reverse this get to back
the shl to fold into SHXADD.

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[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC

Some more complex cases require checking the relationship of
operands on different nodes of the match. They also require
additional

[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC

Some more complex cases require checking the relationship of
operands on different nodes of the match. They also require
additional instructions to be created. Using a ComplexPattern
gives us that flexibility.

I'll be adding another pattern in a future patch.

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[RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.

This allows us to fold global and constant pool addresses into
load/store during isel instead of in the post-isel peephole. I
did not copy the ali

[RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.

This allows us to fold global and constant pool addresses into
load/store during isel instead of in the post-isel peephole. I
did not copy the alignment check for ConsantPoolSDNode because it
wasn't tested.

This is a step towards being able to remove the post-isel
peephole.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D128738

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[RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).

where C2 has 32 leading zeros and C3 trailing zeros.

When the shl is used by an add C is 1,2 or 3, we end up matching
(add (shl X, C

[RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).

where C2 has 32 leading zeros and C3 trailing zeros.

When the shl is used by an add C is 1,2 or 3, we end up matching
(add (shl X, C), Y) first. This leaves an and with a constant that
is harder to materialize.

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[RISCV][NFC] Simplify condition of IsTU.

Just simplify code.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D128972

[RISCV] Considering existing offset in the alignment when folding ADDIs into load/store.

getPointerAlignment and ConstantPoolSDNode::getAlign only consider
the alignment of the object. If we already

[RISCV] Considering existing offset in the alignment when folding ADDIs into load/store.

getPointerAlignment and ConstantPoolSDNode::getAlign only consider
the alignment of the object. If we already have a non-zero offset
into the offset that may have reduced the alignment.

Since the base pointer will become an LUI with the old offset, we
need to be sure the new offset fits in the alignment of the address
that will be used to create the LUI immediate.

I'm not sure it is possible to have a non-zero offset in the
GlobalAddressSDNode or ConstantPoolSDNode at this point today so this
may only be a theoretical bug.

Differential Revision: https://reviews.llvm.org/D129006

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[RISCV] Avoid repeated code in SelectAddrRegImm. NFC

[RISCV] Remove an unnecessary copy of X0 in selectShiftMask.

We know which instruction we're emitting so its ok to directly
encode X0 into the instruction. We only need to create a copy when
a const

[RISCV] Remove an unnecessary copy of X0 in selectShiftMask.

We know which instruction we're emitting so its ok to directly
encode X0 into the instruction. We only need to create a copy when
a constant 0 is selected without context of what instructions uses it.

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[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.

Only handle immediates that would produce an ADDI or ADDIW of Lo12
as the final instruction in their materialization.

A

[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.

Only handle immediates that would produce an ADDI or ADDIW of Lo12
as the final instruction in their materialization.

As the test change show this removes immediates that materialize
with lui+addiw that is not the same as lui+addi.

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[RISCV] Replace some uses of XLenVT in RISCVDAGToDAGISel::Select with the original Node VT. NFCI

These should contain the same thing, but we aren't consistent about
which we use.

Since we call Repl

[RISCV] Replace some uses of XLenVT in RISCVDAGToDAGISel::Select with the original Node VT. NFCI

These should contain the same thing, but we aren't consistent about
which we use.

Since we call ReplaceNode, it seems more correct to use the initial VT.

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[RISCV] Use getVTList to simplify creation of vleff MachineSDNode. NFC

We don't need to pass the 3 VTs separately, we already have a list
available to us.

[RISCV] Use the VT passed into selectImm instead of XLenVT. NFCI

I think the VT pased in will always be XLen.

[RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).

If C2 has 32 leading zeros and C3 trailing zeros.