64   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);  in emitSCSPrologue()
69   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))  in emitSCSPrologue()
74   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))  in emitSCSPrologue()
114   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);  in emitSCSEpilogue()
119   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))  in emitSCSEpilogue()
124   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))  in emitSCSEpilogue()
142   Register MaxReg = RISCV::NoRegister;  in getLibCallID()
149   if (MaxReg == RISCV::NoRegister)  in getLibCallID()
155   case /*s11*/ RISCV::X27: return 12;  in getLibCallID()
156   case /*s10*/ RISCV::X26: return 11;  in getLibCallID()
157   case /*s9*/  RISCV::X25: return 10;  in getLibCallID()
158   case /*s8*/  RISCV::X24: return 9;  in getLibCallID()
159   case /*s7*/  RISCV::X23: return 8;  in getLibCallID()
160   case /*s6*/  RISCV::X22: return 7;  in getLibCallID()
161   case /*s5*/  RISCV::X21: return 6;  in getLibCallID()
162   case /*s4*/  RISCV::X20: return 5;  in getLibCallID()
163   case /*s3*/  RISCV::X19: return 4;  in getLibCallID()
164   case /*s2*/  RISCV::X18: return 3;  in getLibCallID()
165   case /*s1*/  RISCV::X9:  return 2;  in getLibCallID()
166   case /*s0*/  RISCV::X8:  return 1;  in getLibCallID()
167   case /*ra*/  RISCV::X1:  return 0;  in getLibCallID()
304     BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)  in adjustReg()
322     BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)  in adjustReg()
326     BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)  in adjustReg()
333   unsigned Opc = RISCV::ADD;  in adjustReg()
336     Opc = RISCV::SUB;  in adjustReg()
339   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);  in adjustReg()
348 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }  in getFPReg()
351 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }  in getSPReg()
377   unsigned Opc = RISCV::ADD;  in adjustStackForRVV()
380     Opc = RISCV::SUB;  in adjustStackForRVV()
563         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)  in emitPrologue()
570             MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);  in emitPrologue()
571         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)  in emitPrologue()
575         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)  in emitPrologue()
585         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)  in emitPrologue()
716     FrameReg = RISCV::X2;  in getFrameIndexReference()
763       FrameReg = RISCV::X2;  in getFrameIndexReference()
863     SavedRegs.set(RISCV::X1);  in determineCalleeSaves()
864     SavedRegs.set(RISCV::X8);  in determineCalleeSaves()
877     static const MCPhysReg CSRegs[] = { RISCV::X1,      /* ra */  in determineCalleeSaves()
878       RISCV::X5, RISCV::X6, RISCV::X7,                  /* t0-t2 */  in determineCalleeSaves()
879       RISCV::X10, RISCV::X11,                           /* a0-a1, a2-a7 */  in determineCalleeSaves()
880       RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,  in determineCalleeSaves()
881       RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */  in determineCalleeSaves()
893         if (RISCV::FPR16RegClass.contains(Regs[i]) ||  in determineCalleeSaves()
894             RISCV::FPR32RegClass.contains(Regs[i]) ||  in determineCalleeSaves()
895             RISCV::FPR64RegClass.contains(Regs[i]))  in determineCalleeSaves()
977       bool IsRVVSpill = RISCV::isRVVSpill(MI);  in getScavSlotsNumForRVV()
988         } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {  in getScavSlotsNumForRVV()
1004   const TargetRegisterClass *RC = &RISCV::GPRRegClass;  in processFunctionBeforeFrameFinalized()
1086   Register SPReg = RISCV::X2;  in eliminateCallFramePseudoInstr()
1101       if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)  in eliminateCallFramePseudoInstr()
1163     BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)  in spillCalleeSavedRegisters()
1215         BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))  in restoreCalleeSavedRegisters()
1221     if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {  in restoreCalleeSavedRegisters()
1252   return !RS.isRegUsed(RISCV::X5);  in canUseAsPrologue()