Lines Matching refs:RISCV
87 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
90 addRegisterClass(MVT::f16, &RISCV::FPR16RegClass); in RISCVTargetLowering()
92 addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); in RISCVTargetLowering()
94 addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); in RISCVTargetLowering()
117 unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELEN(); in RISCVTargetLowering()
123 if (Size <= RISCV::RVVBitsPerBlock) in RISCVTargetLowering()
124 RC = &RISCV::VRRegClass; in RISCVTargetLowering()
125 else if (Size == 2 * RISCV::RVVBitsPerBlock) in RISCVTargetLowering()
126 RC = &RISCV::VRM2RegClass; in RISCVTargetLowering()
127 else if (Size == 4 * RISCV::RVVBitsPerBlock) in RISCVTargetLowering()
128 RC = &RISCV::VRM4RegClass; in RISCVTargetLowering()
129 else if (Size == 8 * RISCV::RVVBitsPerBlock) in RISCVTargetLowering()
130 RC = &RISCV::VRM8RegClass; in RISCVTargetLowering()
178 setStackPointerRegisterToSaveRestore(RISCV::X2); in RISCVTargetLowering()
1480 return RISCV::VRRegClassID; in getRegClassIDForLMUL()
1482 return RISCV::VRM2RegClassID; in getRegClassIDForLMUL()
1484 return RISCV::VRM4RegClassID; in getRegClassIDForLMUL()
1486 return RISCV::VRM8RegClassID; in getRegClassIDForLMUL()
1496 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in getSubregIndexByMVT()
1498 return RISCV::sub_vrm1_0 + Index; in getSubregIndexByMVT()
1501 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in getSubregIndexByMVT()
1503 return RISCV::sub_vrm2_0 + Index; in getSubregIndexByMVT()
1506 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in getSubregIndexByMVT()
1508 return RISCV::sub_vrm4_0 + Index; in getSubregIndexByMVT()
1515 return RISCV::VRRegClassID; in getRegClassIDForVecVT()
1528 static_assert((RISCV::VRM8RegClassID > RISCV::VRM4RegClassID && in decomposeSubvectorInsertExtractToSubRegs()
1529 RISCV::VRM4RegClassID > RISCV::VRM2RegClassID && in decomposeSubvectorInsertExtractToSubRegs()
1530 RISCV::VRM2RegClassID > RISCV::VRRegClassID), in decomposeSubvectorInsertExtractToSubRegs()
1540 unsigned SubRegIdx = RISCV::NoSubRegister; in decomposeSubvectorInsertExtractToSubRegs()
1542 {RISCV::VRM4RegClassID, RISCV::VRM2RegClassID, RISCV::VRRegClassID}) in decomposeSubvectorInsertExtractToSubRegs()
1694 (VT.getVectorNumElements() * RISCV::RVVBitsPerBlock) / MinVLen; in getContainerForFixedLengthVector()
1695 NumElts = std::max(NumElts, RISCV::RVVBitsPerBlock / MaxELen); in getContainerForFixedLengthVector()
1763 : DAG.getRegister(RISCV::X0, XLenVT); in getDefaultVLOps()
2413 DAG.getRegister(RISCV::X0, MVT::i32)); in splatPartsI64WithVL()
2648 DAG.getRegister(RISCV::X0, XLenVT), in lowerVECTOR_SHUFFLE()
3267 static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!"); in LowerOperation()
3268 if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock) in LowerOperation()
3801 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); in getStaticTLSAddr()
3817 SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT); in getStaticTLSAddr()
4191 Lo, DAG.getRegister(RISCV::X0, MVT::i32)); in lowerSPLAT_VECTOR_PARTS()
4199 DAG.getRegister(RISCV::X0, MVT::i32)); in lowerSPLAT_VECTOR_PARTS()
4204 DAG.getRegister(RISCV::X0, MVT::i32)); in lowerSPLAT_VECTOR_PARTS()
4848 return DAG.getRegister(RISCV::X4, PtrVT); in LowerINTRINSIC_WO_CHAIN()
5111 RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits()); in getLMUL1VT()
5742 if (MinSize == (8 * RISCV::RVVBitsPerBlock)) { in lowerVECTOR_REVERSE()
5783 VLMinus1, DAG.getRegister(RISCV::X0, XLenVT)); in lowerVECTOR_REVERSE()
5825 TrueMask, DAG.getRegister(RISCV::X0, XLenVT)); in lowerVECTOR_SPLICE()
9231 DAG.getRegister(RISCV::X0, Subtarget.getXLenVT())); in PerformDAGCombine()
9769 assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction"); in emitReadCycleWidePseudo()
9800 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); in emitReadCycleWidePseudo()
9806 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg) in emitReadCycleWidePseudo()
9808 .addReg(RISCV::X0); in emitReadCycleWidePseudo()
9809 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg) in emitReadCycleWidePseudo()
9811 .addReg(RISCV::X0); in emitReadCycleWidePseudo()
9812 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg) in emitReadCycleWidePseudo()
9814 .addReg(RISCV::X0); in emitReadCycleWidePseudo()
9816 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in emitReadCycleWidePseudo()
9831 assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction"); in emitSplitF64Pseudo()
9840 const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass; in emitSplitF64Pseudo()
9850 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) in emitSplitF64Pseudo()
9854 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
9864 assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo && in emitBuildPairF64Pseudo()
9874 const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; in emitBuildPairF64Pseudo()
9882 BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) in emitBuildPairF64Pseudo()
9887 BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) in emitBuildPairF64Pseudo()
9901 case RISCV::Select_GPR_Using_CC_GPR: in isSelectPseudo()
9902 case RISCV::Select_FPR16_Using_CC_GPR: in isSelectPseudo()
9903 case RISCV::Select_FPR32_Using_CC_GPR: in isSelectPseudo()
9904 case RISCV::Select_FPR64_Using_CC_GPR: in isSelectPseudo()
9917 Register SavedFFlags = MRI.createVirtualRegister(&RISCV::GPRRegClass); in emitQuietFCMP()
9921 BuildMI(*BB, MI, DL, TII.get(RISCV::ReadFFLAGS), SavedFFlags); in emitQuietFCMP()
9930 BuildMI(*BB, MI, DL, TII.get(RISCV::WriteFFLAGS)) in emitQuietFCMP()
9934 auto MIB2 = BuildMI(*BB, MI, DL, TII.get(EqOpcode), RISCV::X0) in emitQuietFCMP()
10034 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII.get(RISCV::PHI), DestReg) in EmitLoweredCascadedSelect()
10089 if (MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR && Next != BB->end() && in emitSelectPseudo()
10167 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg()) in emitSelectPseudo()
10187 case RISCV::ReadCycleWide: in EmitInstrWithCustomInserter()
10191 case RISCV::Select_GPR_Using_CC_GPR: in EmitInstrWithCustomInserter()
10192 case RISCV::Select_FPR16_Using_CC_GPR: in EmitInstrWithCustomInserter()
10193 case RISCV::Select_FPR32_Using_CC_GPR: in EmitInstrWithCustomInserter()
10194 case RISCV::Select_FPR64_Using_CC_GPR: in EmitInstrWithCustomInserter()
10196 case RISCV::BuildPairF64Pseudo: in EmitInstrWithCustomInserter()
10198 case RISCV::SplitF64Pseudo: in EmitInstrWithCustomInserter()
10200 case RISCV::PseudoQuietFLE_H: in EmitInstrWithCustomInserter()
10201 return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget); in EmitInstrWithCustomInserter()
10202 case RISCV::PseudoQuietFLT_H: in EmitInstrWithCustomInserter()
10203 return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget); in EmitInstrWithCustomInserter()
10204 case RISCV::PseudoQuietFLE_S: in EmitInstrWithCustomInserter()
10205 return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget); in EmitInstrWithCustomInserter()
10206 case RISCV::PseudoQuietFLT_S: in EmitInstrWithCustomInserter()
10207 return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget); in EmitInstrWithCustomInserter()
10208 case RISCV::PseudoQuietFLE_D: in EmitInstrWithCustomInserter()
10209 return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget); in EmitInstrWithCustomInserter()
10210 case RISCV::PseudoQuietFLT_D: in EmitInstrWithCustomInserter()
10211 return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget); in EmitInstrWithCustomInserter()
10219 auto Idx = RISCV::getNamedOperandIdx(Opc, RISCV::OpName::frm); in AdjustInstrPostInstrSelection()
10225 if (MI.readsRegister(RISCV::FRM)) in AdjustInstrPostInstrSelection()
10228 MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false, /*isImp*/ true)); in AdjustInstrPostInstrSelection()
10257 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13,
10258 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
10261 RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H,
10262 RISCV::F14_H, RISCV::F15_H, RISCV::F16_H, RISCV::F17_H
10265 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
10266 RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
10269 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
10270 RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
10274 RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13,
10275 RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
10276 RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23};
10277 static const MCPhysReg ArgVRM2s[] = {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2,
10278 RISCV::V14M2, RISCV::V16M2, RISCV::V18M2,
10279 RISCV::V20M2, RISCV::V22M2};
10280 static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4,
10281 RISCV::V20M4};
10282 static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8};
10327 if (RC == &RISCV::VRRegClass) { in allocateRVVReg()
10332 return State.AllocateReg(RISCV::V0); in allocateRVVReg()
10335 if (RC == &RISCV::VRM2RegClass) in allocateRVVReg()
10337 if (RC == &RISCV::VRM4RegClass) in allocateRVVReg()
10339 if (RC == &RISCV::VRM8RegClass) in allocateRVVReg()
10752 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); in unpackF64OnRV32DSoftABI()
10756 if (VA.getLocReg() == RISCV::X17) { in unpackF64OnRV32DSoftABI()
10764 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass); in unpackF64OnRV32DSoftABI()
10783 RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, in CC_RISCV_FastCC()
10784 RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28, in CC_RISCV_FastCC()
10785 RISCV::X29, RISCV::X30, RISCV::X31}; in CC_RISCV_FastCC()
10796 RISCV::F10_H, RISCV::F11_H, RISCV::F12_H, RISCV::F13_H, RISCV::F14_H, in CC_RISCV_FastCC()
10797 RISCV::F15_H, RISCV::F16_H, RISCV::F17_H, RISCV::F0_H, RISCV::F1_H, in CC_RISCV_FastCC()
10798 RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H, in CC_RISCV_FastCC()
10799 RISCV::F7_H, RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H}; in CC_RISCV_FastCC()
10808 RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, in CC_RISCV_FastCC()
10809 RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F0_F, RISCV::F1_F, in CC_RISCV_FastCC()
10810 RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, in CC_RISCV_FastCC()
10811 RISCV::F7_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F}; in CC_RISCV_FastCC()
10820 RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, in CC_RISCV_FastCC()
10821 RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F0_D, RISCV::F1_D, in CC_RISCV_FastCC()
10822 RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, in CC_RISCV_FastCC()
10823 RISCV::F7_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D}; in CC_RISCV_FastCC()
10883 RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, in CC_RISCV_GHC()
10884 RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27}; in CC_RISCV_GHC()
10894 static const MCPhysReg FPR32List[] = {RISCV::F8_F, RISCV::F9_F, in CC_RISCV_GHC()
10895 RISCV::F18_F, RISCV::F19_F, in CC_RISCV_GHC()
10896 RISCV::F20_F, RISCV::F21_F}; in CC_RISCV_GHC()
10906 static const MCPhysReg FPR64List[] = {RISCV::F22_D, RISCV::F23_D, in CC_RISCV_GHC()
10907 RISCV::F24_D, RISCV::F25_D, in CC_RISCV_GHC()
10908 RISCV::F26_D, RISCV::F27_D}; in CC_RISCV_GHC()
10934 if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] || in LowerFormalArguments()
10935 !MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD]) in LowerFormalArguments()
11013 const TargetRegisterClass *RC = &RISCV::GPRRegClass; in LowerFormalArguments()
11243 if (RegLo == RISCV::X17) { in LowerCall()
11247 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); in LowerCall()
11253 assert(RegLo < RISCV::X31 && "Invalid register pair"); in LowerCall()
11328 StackPtr = DAG.getCopyFromReg(Chain, DL, RISCV::X2, PtrVT); in LowerCall()
11356 MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(RISCV::X1)) in LowerCall()
11516 assert(RegLo < RISCV::X31 && "Invalid register pair"); in LowerReturn()
11801 return std::make_pair(0U, &RISCV::GPRRegClass); in getRegForInlineAsmConstraint()
11804 return std::make_pair(0U, &RISCV::FPR16RegClass); in getRegForInlineAsmConstraint()
11806 return std::make_pair(0U, &RISCV::FPR32RegClass); in getRegForInlineAsmConstraint()
11808 return std::make_pair(0U, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
11814 for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass, in getRegForInlineAsmConstraint()
11815 &RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) { in getRegForInlineAsmConstraint()
11820 if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
11821 return std::make_pair(0U, &RISCV::VMV0RegClass); in getRegForInlineAsmConstraint()
11829 .Case("{zero}", RISCV::X0) in getRegForInlineAsmConstraint()
11830 .Case("{ra}", RISCV::X1) in getRegForInlineAsmConstraint()
11831 .Case("{sp}", RISCV::X2) in getRegForInlineAsmConstraint()
11832 .Case("{gp}", RISCV::X3) in getRegForInlineAsmConstraint()
11833 .Case("{tp}", RISCV::X4) in getRegForInlineAsmConstraint()
11834 .Case("{t0}", RISCV::X5) in getRegForInlineAsmConstraint()
11835 .Case("{t1}", RISCV::X6) in getRegForInlineAsmConstraint()
11836 .Case("{t2}", RISCV::X7) in getRegForInlineAsmConstraint()
11837 .Cases("{s0}", "{fp}", RISCV::X8) in getRegForInlineAsmConstraint()
11838 .Case("{s1}", RISCV::X9) in getRegForInlineAsmConstraint()
11839 .Case("{a0}", RISCV::X10) in getRegForInlineAsmConstraint()
11840 .Case("{a1}", RISCV::X11) in getRegForInlineAsmConstraint()
11841 .Case("{a2}", RISCV::X12) in getRegForInlineAsmConstraint()
11842 .Case("{a3}", RISCV::X13) in getRegForInlineAsmConstraint()
11843 .Case("{a4}", RISCV::X14) in getRegForInlineAsmConstraint()
11844 .Case("{a5}", RISCV::X15) in getRegForInlineAsmConstraint()
11845 .Case("{a6}", RISCV::X16) in getRegForInlineAsmConstraint()
11846 .Case("{a7}", RISCV::X17) in getRegForInlineAsmConstraint()
11847 .Case("{s2}", RISCV::X18) in getRegForInlineAsmConstraint()
11848 .Case("{s3}", RISCV::X19) in getRegForInlineAsmConstraint()
11849 .Case("{s4}", RISCV::X20) in getRegForInlineAsmConstraint()
11850 .Case("{s5}", RISCV::X21) in getRegForInlineAsmConstraint()
11851 .Case("{s6}", RISCV::X22) in getRegForInlineAsmConstraint()
11852 .Case("{s7}", RISCV::X23) in getRegForInlineAsmConstraint()
11853 .Case("{s8}", RISCV::X24) in getRegForInlineAsmConstraint()
11854 .Case("{s9}", RISCV::X25) in getRegForInlineAsmConstraint()
11855 .Case("{s10}", RISCV::X26) in getRegForInlineAsmConstraint()
11856 .Case("{s11}", RISCV::X27) in getRegForInlineAsmConstraint()
11857 .Case("{t3}", RISCV::X28) in getRegForInlineAsmConstraint()
11858 .Case("{t4}", RISCV::X29) in getRegForInlineAsmConstraint()
11859 .Case("{t5}", RISCV::X30) in getRegForInlineAsmConstraint()
11860 .Case("{t6}", RISCV::X31) in getRegForInlineAsmConstraint()
11861 .Default(RISCV::NoRegister); in getRegForInlineAsmConstraint()
11862 if (XRegFromAlias != RISCV::NoRegister) in getRegForInlineAsmConstraint()
11863 return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass); in getRegForInlineAsmConstraint()
11874 .Cases("{f0}", "{ft0}", RISCV::F0_F) in getRegForInlineAsmConstraint()
11875 .Cases("{f1}", "{ft1}", RISCV::F1_F) in getRegForInlineAsmConstraint()
11876 .Cases("{f2}", "{ft2}", RISCV::F2_F) in getRegForInlineAsmConstraint()
11877 .Cases("{f3}", "{ft3}", RISCV::F3_F) in getRegForInlineAsmConstraint()
11878 .Cases("{f4}", "{ft4}", RISCV::F4_F) in getRegForInlineAsmConstraint()
11879 .Cases("{f5}", "{ft5}", RISCV::F5_F) in getRegForInlineAsmConstraint()
11880 .Cases("{f6}", "{ft6}", RISCV::F6_F) in getRegForInlineAsmConstraint()
11881 .Cases("{f7}", "{ft7}", RISCV::F7_F) in getRegForInlineAsmConstraint()
11882 .Cases("{f8}", "{fs0}", RISCV::F8_F) in getRegForInlineAsmConstraint()
11883 .Cases("{f9}", "{fs1}", RISCV::F9_F) in getRegForInlineAsmConstraint()
11884 .Cases("{f10}", "{fa0}", RISCV::F10_F) in getRegForInlineAsmConstraint()
11885 .Cases("{f11}", "{fa1}", RISCV::F11_F) in getRegForInlineAsmConstraint()
11886 .Cases("{f12}", "{fa2}", RISCV::F12_F) in getRegForInlineAsmConstraint()
11887 .Cases("{f13}", "{fa3}", RISCV::F13_F) in getRegForInlineAsmConstraint()
11888 .Cases("{f14}", "{fa4}", RISCV::F14_F) in getRegForInlineAsmConstraint()
11889 .Cases("{f15}", "{fa5}", RISCV::F15_F) in getRegForInlineAsmConstraint()
11890 .Cases("{f16}", "{fa6}", RISCV::F16_F) in getRegForInlineAsmConstraint()
11891 .Cases("{f17}", "{fa7}", RISCV::F17_F) in getRegForInlineAsmConstraint()
11892 .Cases("{f18}", "{fs2}", RISCV::F18_F) in getRegForInlineAsmConstraint()
11893 .Cases("{f19}", "{fs3}", RISCV::F19_F) in getRegForInlineAsmConstraint()
11894 .Cases("{f20}", "{fs4}", RISCV::F20_F) in getRegForInlineAsmConstraint()
11895 .Cases("{f21}", "{fs5}", RISCV::F21_F) in getRegForInlineAsmConstraint()
11896 .Cases("{f22}", "{fs6}", RISCV::F22_F) in getRegForInlineAsmConstraint()
11897 .Cases("{f23}", "{fs7}", RISCV::F23_F) in getRegForInlineAsmConstraint()
11898 .Cases("{f24}", "{fs8}", RISCV::F24_F) in getRegForInlineAsmConstraint()
11899 .Cases("{f25}", "{fs9}", RISCV::F25_F) in getRegForInlineAsmConstraint()
11900 .Cases("{f26}", "{fs10}", RISCV::F26_F) in getRegForInlineAsmConstraint()
11901 .Cases("{f27}", "{fs11}", RISCV::F27_F) in getRegForInlineAsmConstraint()
11902 .Cases("{f28}", "{ft8}", RISCV::F28_F) in getRegForInlineAsmConstraint()
11903 .Cases("{f29}", "{ft9}", RISCV::F29_F) in getRegForInlineAsmConstraint()
11904 .Cases("{f30}", "{ft10}", RISCV::F30_F) in getRegForInlineAsmConstraint()
11905 .Cases("{f31}", "{ft11}", RISCV::F31_F) in getRegForInlineAsmConstraint()
11906 .Default(RISCV::NoRegister); in getRegForInlineAsmConstraint()
11907 if (FReg != RISCV::NoRegister) { in getRegForInlineAsmConstraint()
11908 assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
11910 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
11911 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint()
11912 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
11915 return std::make_pair(FReg, &RISCV::FPR32RegClass); in getRegForInlineAsmConstraint()
11917 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
11918 unsigned HReg = RISCV::F0_H + RegNo; in getRegForInlineAsmConstraint()
11919 return std::make_pair(HReg, &RISCV::FPR16RegClass); in getRegForInlineAsmConstraint()
11926 .Case("{v0}", RISCV::V0) in getRegForInlineAsmConstraint()
11927 .Case("{v1}", RISCV::V1) in getRegForInlineAsmConstraint()
11928 .Case("{v2}", RISCV::V2) in getRegForInlineAsmConstraint()
11929 .Case("{v3}", RISCV::V3) in getRegForInlineAsmConstraint()
11930 .Case("{v4}", RISCV::V4) in getRegForInlineAsmConstraint()
11931 .Case("{v5}", RISCV::V5) in getRegForInlineAsmConstraint()
11932 .Case("{v6}", RISCV::V6) in getRegForInlineAsmConstraint()
11933 .Case("{v7}", RISCV::V7) in getRegForInlineAsmConstraint()
11934 .Case("{v8}", RISCV::V8) in getRegForInlineAsmConstraint()
11935 .Case("{v9}", RISCV::V9) in getRegForInlineAsmConstraint()
11936 .Case("{v10}", RISCV::V10) in getRegForInlineAsmConstraint()
11937 .Case("{v11}", RISCV::V11) in getRegForInlineAsmConstraint()
11938 .Case("{v12}", RISCV::V12) in getRegForInlineAsmConstraint()
11939 .Case("{v13}", RISCV::V13) in getRegForInlineAsmConstraint()
11940 .Case("{v14}", RISCV::V14) in getRegForInlineAsmConstraint()
11941 .Case("{v15}", RISCV::V15) in getRegForInlineAsmConstraint()
11942 .Case("{v16}", RISCV::V16) in getRegForInlineAsmConstraint()
11943 .Case("{v17}", RISCV::V17) in getRegForInlineAsmConstraint()
11944 .Case("{v18}", RISCV::V18) in getRegForInlineAsmConstraint()
11945 .Case("{v19}", RISCV::V19) in getRegForInlineAsmConstraint()
11946 .Case("{v20}", RISCV::V20) in getRegForInlineAsmConstraint()
11947 .Case("{v21}", RISCV::V21) in getRegForInlineAsmConstraint()
11948 .Case("{v22}", RISCV::V22) in getRegForInlineAsmConstraint()
11949 .Case("{v23}", RISCV::V23) in getRegForInlineAsmConstraint()
11950 .Case("{v24}", RISCV::V24) in getRegForInlineAsmConstraint()
11951 .Case("{v25}", RISCV::V25) in getRegForInlineAsmConstraint()
11952 .Case("{v26}", RISCV::V26) in getRegForInlineAsmConstraint()
11953 .Case("{v27}", RISCV::V27) in getRegForInlineAsmConstraint()
11954 .Case("{v28}", RISCV::V28) in getRegForInlineAsmConstraint()
11955 .Case("{v29}", RISCV::V29) in getRegForInlineAsmConstraint()
11956 .Case("{v30}", RISCV::V30) in getRegForInlineAsmConstraint()
11957 .Case("{v31}", RISCV::V31) in getRegForInlineAsmConstraint()
11958 .Default(RISCV::NoRegister); in getRegForInlineAsmConstraint()
11959 if (VReg != RISCV::NoRegister) { in getRegForInlineAsmConstraint()
11960 if (TRI->isTypeLegalForClass(RISCV::VMRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
11961 return std::make_pair(VReg, &RISCV::VMRegClass); in getRegForInlineAsmConstraint()
11962 if (TRI->isTypeLegalForClass(RISCV::VRRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
11963 return std::make_pair(VReg, &RISCV::VRRegClass); in getRegForInlineAsmConstraint()
11965 {&RISCV::VRM2RegClass, &RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) { in getRegForInlineAsmConstraint()
11967 VReg = TRI->getMatchingSuperReg(VReg, RISCV::sub_vrm1_0, RC); in getRegForInlineAsmConstraint()
11980 if (Res.second == &RISCV::GPRF16RegClass || in getRegForInlineAsmConstraint()
11981 Res.second == &RISCV::GPRF32RegClass || in getRegForInlineAsmConstraint()
11982 Res.second == &RISCV::GPRF64RegClass) in getRegForInlineAsmConstraint()
11983 return std::make_pair(Res.first, &RISCV::GPRRegClass); in getRegForInlineAsmConstraint()
12254 static_assert(RISCV::RVVBitsPerBlock == 64, in isVScaleKnownToBeAPowerOfTwo()
12282 return RISCV::X10; in getExceptionPointerRegister()
12287 return RISCV::X11; in getExceptionSelectorRegister()
12549 if (Reg == RISCV::NoRegister) in getRegisterByName()
12551 if (Reg == RISCV::NoRegister) in getRegisterByName()