Lines Matching refs:RISCV

24     case RISCV::SLLI:  in getInstSeqCost()
25 case RISCV::SRLI: in getInstSeqCost()
28 case RISCV::ADDI: in getInstSeqCost()
29 case RISCV::ADDIW: in getInstSeqCost()
30 case RISCV::LUI: in getInstSeqCost()
51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in generateInstSeqImpl()
65 Res.push_back(RISCVMatInt::Inst(RISCV::LUI, Hi20)); in generateInstSeqImpl()
68 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
77 if (ActiveFeatures[RISCV::FeatureStdExtZbs] && isPowerOf2_64(Val)) { in generateInstSeqImpl()
78 Res.push_back(RISCVMatInt::Inst(RISCV::BSETI, Log2_64(Val))); in generateInstSeqImpl()
124 ActiveFeatures[RISCV::FeatureStdExtZba]) { in generateInstSeqImpl()
135 ActiveFeatures[RISCV::FeatureStdExtZba]) { in generateInstSeqImpl()
148 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI_UW, ShiftAmount)); in generateInstSeqImpl()
150 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeqImpl()
154 Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeqImpl()
188 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SLLI, TrailingZeros)); in generateInstSeq()
202 assert(ActiveFeatures[RISCV::Feature64Bit] && in generateInstSeq()
213 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, LeadingZeros)); in generateInstSeq()
227 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, LeadingZeros)); in generateInstSeq()
239 if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureStdExtZba]) { in generateInstSeq()
244 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADD_UW, 0)); in generateInstSeq()
257 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) { in generateInstSeq()
258 assert(ActiveFeatures[RISCV::Feature64Bit] && in generateInstSeq()
270 Opc = RISCV::BCLRI; in generateInstSeq()
273 Opc = RISCV::BSETI; in generateInstSeq()
294 Opc = RISCV::BSETI; in generateInstSeq()
296 Opc = RISCV::BCLRI; in generateInstSeq()
312 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZba]) { in generateInstSeq()
313 assert(ActiveFeatures[RISCV::Feature64Bit] && in generateInstSeq()
321 Opc = RISCV::SH1ADD; in generateInstSeq()
324 Opc = RISCV::SH2ADD; in generateInstSeq()
327 Opc = RISCV::SH3ADD; in generateInstSeq()
342 Opc = RISCV::SH1ADD; in generateInstSeq()
345 Opc = RISCV::SH2ADD; in generateInstSeq()
348 Opc = RISCV::SH3ADD; in generateInstSeq()
359 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeq()
367 if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbb]) { in generateInstSeq()
373 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, NegImm12)); in generateInstSeq()
374 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::RORI, Rotate)); in generateInstSeq()
383 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in getIntMatCost()
384 bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC]; in getIntMatCost()
402 case RISCV::LUI: in getOpndKind()
404 case RISCV::ADD_UW: in getOpndKind()
406 case RISCV::SH1ADD: in getOpndKind()
407 case RISCV::SH2ADD: in getOpndKind()
408 case RISCV::SH3ADD: in getOpndKind()
410 case RISCV::ADDI: in getOpndKind()
411 case RISCV::ADDIW: in getOpndKind()
412 case RISCV::SLLI: in getOpndKind()
413 case RISCV::SRLI: in getOpndKind()
414 case RISCV::SLLI_UW: in getOpndKind()
415 case RISCV::RORI: in getOpndKind()
416 case RISCV::BSETI: in getOpndKind()
417 case RISCV::BCLRI: in getOpndKind()