Lines Matching refs:RISCV
31 namespace RISCV { namespace
63 SDValue VL = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT()); in PreprocessISelDAG()
111 CurDAG->getRegister(RISCV::X0, MVT::i64), in PreprocessISelDAG()
161 SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); in selectImmSeq()
170 CurDAG->getRegister(RISCV::X0, VT)); in selectImmSeq()
198 RISCV::VRN2M1RegClassID, RISCV::VRN3M1RegClassID, RISCV::VRN4M1RegClassID, in createTuple()
199 RISCV::VRN5M1RegClassID, RISCV::VRN6M1RegClassID, RISCV::VRN7M1RegClassID, in createTuple()
200 RISCV::VRN8M1RegClassID}; in createTuple()
201 static const unsigned M2TupleRegClassIDs[] = {RISCV::VRN2M2RegClassID, in createTuple()
202 RISCV::VRN3M2RegClassID, in createTuple()
203 RISCV::VRN4M2RegClassID}; in createTuple()
216 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in createTuple()
218 SubReg0 = RISCV::sub_vrm1_0; in createTuple()
222 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in createTuple()
224 SubReg0 = RISCV::sub_vrm2_0; in createTuple()
228 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in createTuple()
230 SubReg0 = RISCV::sub_vrm4_0; in createTuple()
231 RegClassID = RISCV::VRN2M4RegClassID; in createTuple()
267 Chain = CurDAG->getCopyToReg(Chain, DL, RISCV::V0, Mask, SDValue()); in addVectorLoadStoreOperands()
269 Operands.push_back(CurDAG->getRegister(RISCV::V0, Mask.getValueType())); in addVectorLoadStoreOperands()
319 const RISCV::VLSEGPseudo *P = in selectVLSEG()
320 RISCV::getVLSEGPseudo(NF, IsMasked, IsTU, IsStrided, /*FF*/ false, Log2SEW, in selectVLSEG()
363 const RISCV::VLSEGPseudo *P = in selectVLSEGFF()
364 RISCV::getVLSEGPseudo(NF, IsMasked, IsTU, /*Strided*/ false, /*FF*/ true, in selectVLSEGFF()
418 const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( in selectVLXSEG()
459 const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo( in selectVSSEG()
500 const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo( in selectVSXSEG()
554 unsigned Opcode = RISCV::PseudoVSETVLI; in selectVSETVLI()
556 VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT); in selectVSETVLI()
557 Opcode = RISCV::PseudoVSETVLIX0; in selectVSETVLI()
569 Node, CurDAG->getMachineNode(RISCV::PseudoVSETIVLI, DL, VTs, Ops)); in selectVSETVLI()
602 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, RISCV::X0, XLenVT); in Select()
639 RISCV::SRLIW, DL, VT, N0->getOperand(0), in Select()
642 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
669 RISCV::SRLIW, DL, VT, N0->getOperand(0), in Select()
672 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
696 CurDAG->getMachineNode(RISCV::BEXTI, DL, VT, N0->getOperand(0), in Select()
703 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0), in Select()
706 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
734 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0), in Select()
737 RISCV::SRAI, DL, VT, SDValue(SLLI, 0), in Select()
789 RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT)); in Select()
803 CurDAG->getMachineNode(RISCV::SRAIW, DL, VT, X.getOperand(0), in Select()
806 RISCV::SRLIW, DL, VT, SDValue(SRAIW, 0), in Select()
821 RISCV::SLLI, DL, VT, X, in Select()
824 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
842 RISCV::SLLI_UW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT)); in Select()
850 RISCV::SLLI, DL, VT, X, in Select()
853 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
867 unsigned SrliOpc = RISCV::SRLI; in Select()
871 SrliOpc = RISCV::SRLIW; in Select()
878 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, SDValue(SRLI, 0), in Select()
887 RISCV::SRLIW, DL, VT, X, in Select()
890 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
904 RISCV::SRLI, DL, VT, X, in Select()
907 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, SDValue(SRLI, 0), in Select()
915 RISCV::SRLIW, DL, VT, X, in Select()
918 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
984 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0.getOperand(0), in Select()
986 SDNode *MULHU = CurDAG->getMachineNode(RISCV::MULHU, DL, VT, in Select()
1022 VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \ in Select()
1023 : RISCV::PseudoVMSLT_VX_##suffix; \ in Select()
1024 VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \ in Select()
1025 VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b; \ in Select()
1082 VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \ in Select()
1083 : RISCV::PseudoVMSLT_VX_##suffix; \ in Select()
1084 VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK \ in Select()
1085 : RISCV::PseudoVMSLT_VX_##suffix##_MASK; \ in Select()
1102 VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix; \ in Select()
1103 VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix; \ in Select()
1104 VMOROpcode = RISCV::PseudoVMOR_MM_##suffix; \ in Select()
1151 RISCV::V0, Mask, SDValue()); in Select()
1153 SDValue V0 = CurDAG->getRegister(RISCV::V0, VT); in Select()
1317 const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo( in Select()
1359 const RISCV::VLEPseudo *P = in Select()
1360 RISCV::getVLEPseudo(IsMasked, IsTU, IsStrided, /*FF*/ false, Log2SEW, in Select()
1393 const RISCV::VLEPseudo *P = in Select()
1394 RISCV::getVLEPseudo(IsMasked, IsTU, /*Strided*/ false, /*FF*/ true, in Select()
1517 const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo( in Select()
1550 const RISCV::VSEPseudo *P = RISCV::getVSEPseudo( in Select()
1613 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
1657 if (SubRegIdx == RISCV::NoSubRegister) { in Select()
1698 VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, DL, XLenVT); in Select()
1712 CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW, in Select()
1716 const RISCV::VLEPseudo *P = RISCV::getVLEPseudo( in Select()
1803 CurDAG->getMachineNode(RISCV::LUI, DL, VT, in selectConstantAddr()
1807 Base = CurDAG->getRegister(RISCV::X0, VT); in selectConstantAddr()
1819 if (Seq.back().Opc != RISCV::ADDI) in selectConstantAddr()
1914 CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0), in SelectAddrRegImm()
1932 CurDAG->getMachineNode(RISCV::ADD, DL, VT, Addr.getOperand(0), Base), in SelectAddrRegImm()
1979 SDValue Zero = CurDAG->getRegister(RISCV::X0, VT); in selectShiftMask()
1980 unsigned NegOpc = VT == MVT::i64 ? RISCV::SUBW : RISCV::SUB; in selectShiftMask()
2055 RISCV::SRLI, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2068 RISCV::SRLI, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2096 RISCV::SRLIW, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2108 RISCV::SRLIW, DL, VT, N0.getOperand(0), in selectSHXADDOp()
2151 case RISCV::ADDW: in hasAllNBitUsers()
2152 case RISCV::ADDIW: in hasAllNBitUsers()
2153 case RISCV::SUBW: in hasAllNBitUsers()
2154 case RISCV::MULW: in hasAllNBitUsers()
2155 case RISCV::SLLW: in hasAllNBitUsers()
2156 case RISCV::SLLIW: in hasAllNBitUsers()
2157 case RISCV::SRAW: in hasAllNBitUsers()
2158 case RISCV::SRAIW: in hasAllNBitUsers()
2159 case RISCV::SRLW: in hasAllNBitUsers()
2160 case RISCV::SRLIW: in hasAllNBitUsers()
2161 case RISCV::DIVW: in hasAllNBitUsers()
2162 case RISCV::DIVUW: in hasAllNBitUsers()
2163 case RISCV::REMW: in hasAllNBitUsers()
2164 case RISCV::REMUW: in hasAllNBitUsers()
2165 case RISCV::ROLW: in hasAllNBitUsers()
2166 case RISCV::RORW: in hasAllNBitUsers()
2167 case RISCV::RORIW: in hasAllNBitUsers()
2168 case RISCV::CLZW: in hasAllNBitUsers()
2169 case RISCV::CTZW: in hasAllNBitUsers()
2170 case RISCV::CPOPW: in hasAllNBitUsers()
2171 case RISCV::SLLI_UW: in hasAllNBitUsers()
2172 case RISCV::FMV_W_X: in hasAllNBitUsers()
2173 case RISCV::FCVT_H_W: in hasAllNBitUsers()
2174 case RISCV::FCVT_H_WU: in hasAllNBitUsers()
2175 case RISCV::FCVT_S_W: in hasAllNBitUsers()
2176 case RISCV::FCVT_S_WU: in hasAllNBitUsers()
2177 case RISCV::FCVT_D_W: in hasAllNBitUsers()
2178 case RISCV::FCVT_D_WU: in hasAllNBitUsers()
2182 case RISCV::SLLI: in hasAllNBitUsers()
2187 case RISCV::ANDI: in hasAllNBitUsers()
2191 case RISCV::SEXT_B: in hasAllNBitUsers()
2195 case RISCV::SEXT_H: in hasAllNBitUsers()
2196 case RISCV::FMV_H_X: in hasAllNBitUsers()
2197 case RISCV::ZEXT_H_RV32: in hasAllNBitUsers()
2198 case RISCV::ZEXT_H_RV64: in hasAllNBitUsers()
2202 case RISCV::ADD_UW: in hasAllNBitUsers()
2203 case RISCV::SH1ADD_UW: in hasAllNBitUsers()
2204 case RISCV::SH2ADD_UW: in hasAllNBitUsers()
2205 case RISCV::SH3ADD_UW: in hasAllNBitUsers()
2211 case RISCV::SB: in hasAllNBitUsers()
2215 case RISCV::SH: in hasAllNBitUsers()
2219 case RISCV::SW: in hasAllNBitUsers()
2238 VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N), in selectVLOp()
2241 cast<RegisterSDNode>(N)->getReg() == RISCV::X0) { in selectVLOp()
2246 VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, SDLoc(N), in selectVLOp()
2351 if (N->getMachineOpcode() != RISCV::ADDIW || in doPeepholeSExtW()
2362 case RISCV::ADD: in doPeepholeSExtW()
2363 case RISCV::ADDI: in doPeepholeSExtW()
2364 case RISCV::SUB: in doPeepholeSExtW()
2365 case RISCV::MUL: in doPeepholeSExtW()
2366 case RISCV::SLLI: { in doPeepholeSExtW()
2373 case RISCV::ADD: Opc = RISCV::ADDW; break; in doPeepholeSExtW()
2374 case RISCV::ADDI: Opc = RISCV::ADDIW; break; in doPeepholeSExtW()
2375 case RISCV::SUB: Opc = RISCV::SUBW; break; in doPeepholeSExtW()
2376 case RISCV::MUL: Opc = RISCV::MULW; break; in doPeepholeSExtW()
2377 case RISCV::SLLI: Opc = RISCV::SLLIW; break; in doPeepholeSExtW()
2384 if (N0.getMachineOpcode() == RISCV::SLLI && in doPeepholeSExtW()
2394 case RISCV::ADDW: in doPeepholeSExtW()
2395 case RISCV::ADDIW: in doPeepholeSExtW()
2396 case RISCV::SUBW: in doPeepholeSExtW()
2397 case RISCV::MULW: in doPeepholeSExtW()
2398 case RISCV::SLLIW: in doPeepholeSExtW()
2399 case RISCV::GREVIW: in doPeepholeSExtW()
2400 case RISCV::GORCIW: in doPeepholeSExtW()
2415 const RISCV::RISCVMaskedPseudoInfo *I = in doPeepholeMaskedRVV()
2416 RISCV::getMaskedPseudoInfo(N->getMachineOpcode()); in doPeepholeMaskedRVV()
2424 cast<RegisterSDNode>(N->getOperand(MaskOpIdx))->getReg() != RISCV::V0) in doPeepholeMaskedRVV()
2435 cast<RegisterSDNode>(Glued->getOperand(1))->getReg() != RISCV::V0) in doPeepholeMaskedRVV()
2442 return Opc == RISCV::PseudoVMSET_M_B1 || Opc == RISCV::PseudoVMSET_M_B16 || in doPeepholeMaskedRVV()
2443 Opc == RISCV::PseudoVMSET_M_B2 || Opc == RISCV::PseudoVMSET_M_B32 || in doPeepholeMaskedRVV()
2444 Opc == RISCV::PseudoVMSET_M_B4 || Opc == RISCV::PseudoVMSET_M_B64 || in doPeepholeMaskedRVV()
2445 Opc == RISCV::PseudoVMSET_M_B8; in doPeepholeMaskedRVV()