162   bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);  in lowerRISCVVMachineInstrToMCInst()
182       if (RISCV::VRM2RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
183           RISCV::VRM4RegClass.contains(Reg) ||  in lowerRISCVVMachineInstrToMCInst()
184           RISCV::VRM8RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
185         Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);  in lowerRISCVVMachineInstrToMCInst()
187       } else if (RISCV::FPR16RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
188         Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);  in lowerRISCVVMachineInstrToMCInst()
190       } else if (RISCV::FPR64RegClass.contains(Reg)) {  in lowerRISCVVMachineInstrToMCInst()
191         Reg = TRI->getSubReg(Reg, RISCV::sub_32);  in lowerRISCVVMachineInstrToMCInst()
208     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));  in lowerRISCVVMachineInstrToMCInst()
240   case RISCV::PseudoReadVLENB:  in lowerRISCVMachineInstrToMCInst()
241     OutMI.setOpcode(RISCV::CSRRS);  in lowerRISCVMachineInstrToMCInst()
244     OutMI.addOperand(MCOperand::createReg(RISCV::X0));  in lowerRISCVMachineInstrToMCInst()
246   case RISCV::PseudoReadVL:  in lowerRISCVMachineInstrToMCInst()
247     OutMI.setOpcode(RISCV::CSRRS);  in lowerRISCVMachineInstrToMCInst()
250     OutMI.addOperand(MCOperand::createReg(RISCV::X0));  in lowerRISCVMachineInstrToMCInst()