59   case RISCV::PseudoVMV_S_X_M1:  in isScalarMoveInstr()
60   case RISCV::PseudoVMV_S_X_M2:  in isScalarMoveInstr()
61   case RISCV::PseudoVMV_S_X_M4:  in isScalarMoveInstr()
62   case RISCV::PseudoVMV_S_X_M8:  in isScalarMoveInstr()
63   case RISCV::PseudoVMV_S_X_MF2:  in isScalarMoveInstr()
64   case RISCV::PseudoVMV_S_X_MF4:  in isScalarMoveInstr()
65   case RISCV::PseudoVMV_S_X_MF8:  in isScalarMoveInstr()
66   case RISCV::PseudoVFMV_S_F16_M1:  in isScalarMoveInstr()
67   case RISCV::PseudoVFMV_S_F16_M2:  in isScalarMoveInstr()
68   case RISCV::PseudoVFMV_S_F16_M4:  in isScalarMoveInstr()
69   case RISCV::PseudoVFMV_S_F16_M8:  in isScalarMoveInstr()
70   case RISCV::PseudoVFMV_S_F16_MF2:  in isScalarMoveInstr()
71   case RISCV::PseudoVFMV_S_F16_MF4:  in isScalarMoveInstr()
72   case RISCV::PseudoVFMV_S_F32_M1:  in isScalarMoveInstr()
73   case RISCV::PseudoVFMV_S_F32_M2:  in isScalarMoveInstr()
74   case RISCV::PseudoVFMV_S_F32_M4:  in isScalarMoveInstr()
75   case RISCV::PseudoVFMV_S_F32_M8:  in isScalarMoveInstr()
76   case RISCV::PseudoVFMV_S_F32_MF2:  in isScalarMoveInstr()
77   case RISCV::PseudoVFMV_S_F64_M1:  in isScalarMoveInstr()
78   case RISCV::PseudoVFMV_S_F64_M2:  in isScalarMoveInstr()
79   case RISCV::PseudoVFMV_S_F64_M4:  in isScalarMoveInstr()
80   case RISCV::PseudoVFMV_S_F64_M8:  in isScalarMoveInstr()
91   case RISCV::PseudoVLE8_V_M1:  in getEEWForLoadStore()
92   case RISCV::PseudoVLE8_V_M1_MASK:  in getEEWForLoadStore()
93   case RISCV::PseudoVLE8_V_M2:  in getEEWForLoadStore()
94   case RISCV::PseudoVLE8_V_M2_MASK:  in getEEWForLoadStore()
95   case RISCV::PseudoVLE8_V_M4:  in getEEWForLoadStore()
96   case RISCV::PseudoVLE8_V_M4_MASK:  in getEEWForLoadStore()
97   case RISCV::PseudoVLE8_V_M8:  in getEEWForLoadStore()
98   case RISCV::PseudoVLE8_V_M8_MASK:  in getEEWForLoadStore()
99   case RISCV::PseudoVLE8_V_MF2:  in getEEWForLoadStore()
100   case RISCV::PseudoVLE8_V_MF2_MASK:  in getEEWForLoadStore()
101   case RISCV::PseudoVLE8_V_MF4:  in getEEWForLoadStore()
102   case RISCV::PseudoVLE8_V_MF4_MASK:  in getEEWForLoadStore()
103   case RISCV::PseudoVLE8_V_MF8:  in getEEWForLoadStore()
104   case RISCV::PseudoVLE8_V_MF8_MASK:  in getEEWForLoadStore()
105   case RISCV::PseudoVLSE8_V_M1:  in getEEWForLoadStore()
106   case RISCV::PseudoVLSE8_V_M1_MASK:  in getEEWForLoadStore()
107   case RISCV::PseudoVLSE8_V_M2:  in getEEWForLoadStore()
108   case RISCV::PseudoVLSE8_V_M2_MASK:  in getEEWForLoadStore()
109   case RISCV::PseudoVLSE8_V_M4:  in getEEWForLoadStore()
110   case RISCV::PseudoVLSE8_V_M4_MASK:  in getEEWForLoadStore()
111   case RISCV::PseudoVLSE8_V_M8:  in getEEWForLoadStore()
112   case RISCV::PseudoVLSE8_V_M8_MASK:  in getEEWForLoadStore()
113   case RISCV::PseudoVLSE8_V_MF2:  in getEEWForLoadStore()
114   case RISCV::PseudoVLSE8_V_MF2_MASK:  in getEEWForLoadStore()
115   case RISCV::PseudoVLSE8_V_MF4:  in getEEWForLoadStore()
116   case RISCV::PseudoVLSE8_V_MF4_MASK:  in getEEWForLoadStore()
117   case RISCV::PseudoVLSE8_V_MF8:  in getEEWForLoadStore()
118   case RISCV::PseudoVLSE8_V_MF8_MASK:  in getEEWForLoadStore()
119   case RISCV::PseudoVSE8_V_M1:  in getEEWForLoadStore()
120   case RISCV::PseudoVSE8_V_M1_MASK:  in getEEWForLoadStore()
121   case RISCV::PseudoVSE8_V_M2:  in getEEWForLoadStore()
122   case RISCV::PseudoVSE8_V_M2_MASK:  in getEEWForLoadStore()
123   case RISCV::PseudoVSE8_V_M4:  in getEEWForLoadStore()
124   case RISCV::PseudoVSE8_V_M4_MASK:  in getEEWForLoadStore()
125   case RISCV::PseudoVSE8_V_M8:  in getEEWForLoadStore()
126   case RISCV::PseudoVSE8_V_M8_MASK:  in getEEWForLoadStore()
127   case RISCV::PseudoVSE8_V_MF2:  in getEEWForLoadStore()
128   case RISCV::PseudoVSE8_V_MF2_MASK:  in getEEWForLoadStore()
129   case RISCV::PseudoVSE8_V_MF4:  in getEEWForLoadStore()
130   case RISCV::PseudoVSE8_V_MF4_MASK:  in getEEWForLoadStore()
131   case RISCV::PseudoVSE8_V_MF8:  in getEEWForLoadStore()
132   case RISCV::PseudoVSE8_V_MF8_MASK:  in getEEWForLoadStore()
133   case RISCV::PseudoVSSE8_V_M1:  in getEEWForLoadStore()
134   case RISCV::PseudoVSSE8_V_M1_MASK:  in getEEWForLoadStore()
135   case RISCV::PseudoVSSE8_V_M2:  in getEEWForLoadStore()
136   case RISCV::PseudoVSSE8_V_M2_MASK:  in getEEWForLoadStore()
137   case RISCV::PseudoVSSE8_V_M4:  in getEEWForLoadStore()
138   case RISCV::PseudoVSSE8_V_M4_MASK:  in getEEWForLoadStore()
139   case RISCV::PseudoVSSE8_V_M8:  in getEEWForLoadStore()
140   case RISCV::PseudoVSSE8_V_M8_MASK:  in getEEWForLoadStore()
141   case RISCV::PseudoVSSE8_V_MF2:  in getEEWForLoadStore()
142   case RISCV::PseudoVSSE8_V_MF2_MASK:  in getEEWForLoadStore()
143   case RISCV::PseudoVSSE8_V_MF4:  in getEEWForLoadStore()
144   case RISCV::PseudoVSSE8_V_MF4_MASK:  in getEEWForLoadStore()
145   case RISCV::PseudoVSSE8_V_MF8:  in getEEWForLoadStore()
146   case RISCV::PseudoVSSE8_V_MF8_MASK:  in getEEWForLoadStore()
148   case RISCV::PseudoVLE16_V_M1:  in getEEWForLoadStore()
149   case RISCV::PseudoVLE16_V_M1_MASK:  in getEEWForLoadStore()
150   case RISCV::PseudoVLE16_V_M2:  in getEEWForLoadStore()
151   case RISCV::PseudoVLE16_V_M2_MASK:  in getEEWForLoadStore()
152   case RISCV::PseudoVLE16_V_M4:  in getEEWForLoadStore()
153   case RISCV::PseudoVLE16_V_M4_MASK:  in getEEWForLoadStore()
154   case RISCV::PseudoVLE16_V_M8:  in getEEWForLoadStore()
155   case RISCV::PseudoVLE16_V_M8_MASK:  in getEEWForLoadStore()
156   case RISCV::PseudoVLE16_V_MF2:  in getEEWForLoadStore()
157   case RISCV::PseudoVLE16_V_MF2_MASK:  in getEEWForLoadStore()
158   case RISCV::PseudoVLE16_V_MF4:  in getEEWForLoadStore()
159   case RISCV::PseudoVLE16_V_MF4_MASK:  in getEEWForLoadStore()
160   case RISCV::PseudoVLSE16_V_M1:  in getEEWForLoadStore()
161   case RISCV::PseudoVLSE16_V_M1_MASK:  in getEEWForLoadStore()
162   case RISCV::PseudoVLSE16_V_M2:  in getEEWForLoadStore()
163   case RISCV::PseudoVLSE16_V_M2_MASK:  in getEEWForLoadStore()
164   case RISCV::PseudoVLSE16_V_M4:  in getEEWForLoadStore()
165   case RISCV::PseudoVLSE16_V_M4_MASK:  in getEEWForLoadStore()
166   case RISCV::PseudoVLSE16_V_M8:  in getEEWForLoadStore()
167   case RISCV::PseudoVLSE16_V_M8_MASK:  in getEEWForLoadStore()
168   case RISCV::PseudoVLSE16_V_MF2:  in getEEWForLoadStore()
169   case RISCV::PseudoVLSE16_V_MF2_MASK:  in getEEWForLoadStore()
170   case RISCV::PseudoVLSE16_V_MF4:  in getEEWForLoadStore()
171   case RISCV::PseudoVLSE16_V_MF4_MASK:  in getEEWForLoadStore()
172   case RISCV::PseudoVSE16_V_M1:  in getEEWForLoadStore()
173   case RISCV::PseudoVSE16_V_M1_MASK:  in getEEWForLoadStore()
174   case RISCV::PseudoVSE16_V_M2:  in getEEWForLoadStore()
175   case RISCV::PseudoVSE16_V_M2_MASK:  in getEEWForLoadStore()
176   case RISCV::PseudoVSE16_V_M4:  in getEEWForLoadStore()
177   case RISCV::PseudoVSE16_V_M4_MASK:  in getEEWForLoadStore()
178   case RISCV::PseudoVSE16_V_M8:  in getEEWForLoadStore()
179   case RISCV::PseudoVSE16_V_M8_MASK:  in getEEWForLoadStore()
180   case RISCV::PseudoVSE16_V_MF2:  in getEEWForLoadStore()
181   case RISCV::PseudoVSE16_V_MF2_MASK:  in getEEWForLoadStore()
182   case RISCV::PseudoVSE16_V_MF4:  in getEEWForLoadStore()
183   case RISCV::PseudoVSE16_V_MF4_MASK:  in getEEWForLoadStore()
184   case RISCV::PseudoVSSE16_V_M1:  in getEEWForLoadStore()
185   case RISCV::PseudoVSSE16_V_M1_MASK:  in getEEWForLoadStore()
186   case RISCV::PseudoVSSE16_V_M2:  in getEEWForLoadStore()
187   case RISCV::PseudoVSSE16_V_M2_MASK:  in getEEWForLoadStore()
188   case RISCV::PseudoVSSE16_V_M4:  in getEEWForLoadStore()
189   case RISCV::PseudoVSSE16_V_M4_MASK:  in getEEWForLoadStore()
190   case RISCV::PseudoVSSE16_V_M8:  in getEEWForLoadStore()
191   case RISCV::PseudoVSSE16_V_M8_MASK:  in getEEWForLoadStore()
192   case RISCV::PseudoVSSE16_V_MF2:  in getEEWForLoadStore()
193   case RISCV::PseudoVSSE16_V_MF2_MASK:  in getEEWForLoadStore()
194   case RISCV::PseudoVSSE16_V_MF4:  in getEEWForLoadStore()
195   case RISCV::PseudoVSSE16_V_MF4_MASK:  in getEEWForLoadStore()
197   case RISCV::PseudoVLE32_V_M1:  in getEEWForLoadStore()
198   case RISCV::PseudoVLE32_V_M1_MASK:  in getEEWForLoadStore()
199   case RISCV::PseudoVLE32_V_M2:  in getEEWForLoadStore()
200   case RISCV::PseudoVLE32_V_M2_MASK:  in getEEWForLoadStore()
201   case RISCV::PseudoVLE32_V_M4:  in getEEWForLoadStore()
202   case RISCV::PseudoVLE32_V_M4_MASK:  in getEEWForLoadStore()
203   case RISCV::PseudoVLE32_V_M8:  in getEEWForLoadStore()
204   case RISCV::PseudoVLE32_V_M8_MASK:  in getEEWForLoadStore()
205   case RISCV::PseudoVLE32_V_MF2:  in getEEWForLoadStore()
206   case RISCV::PseudoVLE32_V_MF2_MASK:  in getEEWForLoadStore()
207   case RISCV::PseudoVLSE32_V_M1:  in getEEWForLoadStore()
208   case RISCV::PseudoVLSE32_V_M1_MASK:  in getEEWForLoadStore()
209   case RISCV::PseudoVLSE32_V_M2:  in getEEWForLoadStore()
210   case RISCV::PseudoVLSE32_V_M2_MASK:  in getEEWForLoadStore()
211   case RISCV::PseudoVLSE32_V_M4:  in getEEWForLoadStore()
212   case RISCV::PseudoVLSE32_V_M4_MASK:  in getEEWForLoadStore()
213   case RISCV::PseudoVLSE32_V_M8:  in getEEWForLoadStore()
214   case RISCV::PseudoVLSE32_V_M8_MASK:  in getEEWForLoadStore()
215   case RISCV::PseudoVLSE32_V_MF2:  in getEEWForLoadStore()
216   case RISCV::PseudoVLSE32_V_MF2_MASK:  in getEEWForLoadStore()
217   case RISCV::PseudoVSE32_V_M1:  in getEEWForLoadStore()
218   case RISCV::PseudoVSE32_V_M1_MASK:  in getEEWForLoadStore()
219   case RISCV::PseudoVSE32_V_M2:  in getEEWForLoadStore()
220   case RISCV::PseudoVSE32_V_M2_MASK:  in getEEWForLoadStore()
221   case RISCV::PseudoVSE32_V_M4:  in getEEWForLoadStore()
222   case RISCV::PseudoVSE32_V_M4_MASK:  in getEEWForLoadStore()
223   case RISCV::PseudoVSE32_V_M8:  in getEEWForLoadStore()
224   case RISCV::PseudoVSE32_V_M8_MASK:  in getEEWForLoadStore()
225   case RISCV::PseudoVSE32_V_MF2:  in getEEWForLoadStore()
226   case RISCV::PseudoVSE32_V_MF2_MASK:  in getEEWForLoadStore()
227   case RISCV::PseudoVSSE32_V_M1:  in getEEWForLoadStore()
228   case RISCV::PseudoVSSE32_V_M1_MASK:  in getEEWForLoadStore()
229   case RISCV::PseudoVSSE32_V_M2:  in getEEWForLoadStore()
230   case RISCV::PseudoVSSE32_V_M2_MASK:  in getEEWForLoadStore()
231   case RISCV::PseudoVSSE32_V_M4:  in getEEWForLoadStore()
232   case RISCV::PseudoVSSE32_V_M4_MASK:  in getEEWForLoadStore()
233   case RISCV::PseudoVSSE32_V_M8:  in getEEWForLoadStore()
234   case RISCV::PseudoVSSE32_V_M8_MASK:  in getEEWForLoadStore()
235   case RISCV::PseudoVSSE32_V_MF2:  in getEEWForLoadStore()
236   case RISCV::PseudoVSSE32_V_MF2_MASK:  in getEEWForLoadStore()
238   case RISCV::PseudoVLE64_V_M1:  in getEEWForLoadStore()
239   case RISCV::PseudoVLE64_V_M1_MASK:  in getEEWForLoadStore()
240   case RISCV::PseudoVLE64_V_M2:  in getEEWForLoadStore()
241   case RISCV::PseudoVLE64_V_M2_MASK:  in getEEWForLoadStore()
242   case RISCV::PseudoVLE64_V_M4:  in getEEWForLoadStore()
243   case RISCV::PseudoVLE64_V_M4_MASK:  in getEEWForLoadStore()
244   case RISCV::PseudoVLE64_V_M8:  in getEEWForLoadStore()
245   case RISCV::PseudoVLE64_V_M8_MASK:  in getEEWForLoadStore()
246   case RISCV::PseudoVLSE64_V_M1:  in getEEWForLoadStore()
247   case RISCV::PseudoVLSE64_V_M1_MASK:  in getEEWForLoadStore()
248   case RISCV::PseudoVLSE64_V_M2:  in getEEWForLoadStore()
249   case RISCV::PseudoVLSE64_V_M2_MASK:  in getEEWForLoadStore()
250   case RISCV::PseudoVLSE64_V_M4:  in getEEWForLoadStore()
251   case RISCV::PseudoVLSE64_V_M4_MASK:  in getEEWForLoadStore()
252   case RISCV::PseudoVLSE64_V_M8:  in getEEWForLoadStore()
253   case RISCV::PseudoVLSE64_V_M8_MASK:  in getEEWForLoadStore()
254   case RISCV::PseudoVSE64_V_M1:  in getEEWForLoadStore()
255   case RISCV::PseudoVSE64_V_M1_MASK:  in getEEWForLoadStore()
256   case RISCV::PseudoVSE64_V_M2:  in getEEWForLoadStore()
257   case RISCV::PseudoVSE64_V_M2_MASK:  in getEEWForLoadStore()
258   case RISCV::PseudoVSE64_V_M4:  in getEEWForLoadStore()
259   case RISCV::PseudoVSE64_V_M4_MASK:  in getEEWForLoadStore()
260   case RISCV::PseudoVSE64_V_M8:  in getEEWForLoadStore()
261   case RISCV::PseudoVSE64_V_M8_MASK:  in getEEWForLoadStore()
262   case RISCV::PseudoVSSE64_V_M1:  in getEEWForLoadStore()
263   case RISCV::PseudoVSSE64_V_M1_MASK:  in getEEWForLoadStore()
264   case RISCV::PseudoVSSE64_V_M2:  in getEEWForLoadStore()
265   case RISCV::PseudoVSSE64_V_M2_MASK:  in getEEWForLoadStore()
266   case RISCV::PseudoVSSE64_V_M4:  in getEEWForLoadStore()
267   case RISCV::PseudoVSSE64_V_M4_MASK:  in getEEWForLoadStore()
268   case RISCV::PseudoVSSE64_V_M8:  in getEEWForLoadStore()
269   case RISCV::PseudoVSSE64_V_M8_MASK:  in getEEWForLoadStore()
363   if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VL))  in getDemanded()
365   if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VTYPE))  in getDemanded()
469       return getAVLReg() == RISCV::X0;  in hasNonZeroAVL()
585     if (Require.hasAVLReg() && Require.AVLReg == RISCV::NoRegister)  in isCompatible()
762   return MI.getOpcode() == RISCV::PseudoVSETVLI ||  in INITIALIZE_PASS()
763          MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||  in INITIALIZE_PASS()
764          MI.getOpcode() == RISCV::PseudoVSETIVLI;  in INITIALIZE_PASS()
770   if (MI.getOpcode() != RISCV::PseudoVSETVLIX0)  in isVLPreservingConfig()
772   assert(RISCV::X0 == MI.getOperand(1).getReg());  in isVLPreservingConfig()
773   return RISCV::X0 == MI.getOperand(0).getReg();  in isVLPreservingConfig()
834       if (Imm == RISCV::VLMaxSentinel)  in computeInfoForInstr()
835         InstrInfo.setAVLReg(RISCV::X0);  in computeInfoForInstr()
842     InstrInfo.setAVLReg(RISCV::NoRegister);  in computeInfoForInstr()
869     BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))  in insertVSETVLI()
870         .addReg(RISCV::X0, RegState::Define | RegState::Dead)  in insertVSETVLI()
871         .addReg(RISCV::X0, RegState::Kill)  in insertVSETVLI()
873         .addReg(RISCV::VL, RegState::Implicit);  in insertVSETVLI()
878     BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))  in insertVSETVLI()
879         .addReg(RISCV::X0, RegState::Define | RegState::Dead)  in insertVSETVLI()
886   if (AVLReg == RISCV::NoRegister) {  in insertVSETVLI()
891       BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))  in insertVSETVLI()
892           .addReg(RISCV::X0, RegState::Define | RegState::Dead)  in insertVSETVLI()
893           .addReg(RISCV::X0, RegState::Kill)  in insertVSETVLI()
895           .addReg(RISCV::VL, RegState::Implicit);  in insertVSETVLI()
899     BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))  in insertVSETVLI()
900         .addReg(RISCV::X0, RegState::Define | RegState::Dead)  in insertVSETVLI()
907     MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);  in insertVSETVLI()
912   Register DestReg = RISCV::X0;  in insertVSETVLI()
913   unsigned Opcode = RISCV::PseudoVSETVLI;  in insertVSETVLI()
914   if (AVLReg == RISCV::X0) {  in insertVSETVLI()
915     DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);  in insertVSETVLI()
916     Opcode = RISCV::PseudoVSETVLIX0;  in insertVSETVLI()
928   if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {  in getInfoForVSETVLI()
931     assert(MI.getOpcode() == RISCV::PseudoVSETVLI ||  in getInfoForVSETVLI()
932            MI.getOpcode() == RISCV::PseudoVSETVLIX0);  in getInfoForVSETVLI()
934     assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&  in getInfoForVSETVLI()
1037       (DefInfo.hasAVLImm() || DefInfo.getAVLReg() == RISCV::X0)) {  in transferBefore()
1055   if (RISCV::isFaultFirstLoad(MI)) {  in transferAfter()
1063   if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||  in transferAfter()
1064       MI.modifiesRegister(RISCV::VTYPE))  in transferAfter()
1152   if (!PHI || PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)  in needVSETVLIPHI()
1195       assert(MI.getOperand(3).getReg() == RISCV::VL &&  in emitVSETVLIs()
1196              MI.getOperand(4).getReg() == RISCV::VTYPE &&  in emitVSETVLIs()
1222           VLOp.setReg(RISCV::NoRegister);  in emitVSETVLIs()
1225         MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,  in emitVSETVLIs()
1228       MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,  in emitVSETVLIs()
1232     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||  in emitVSETVLIs()
1233         MI.modifiesRegister(RISCV::VTYPE))  in emitVSETVLIs()
1273     return RISCV::X0 == Info.getAVLReg();  in hasFixedResult()
1422     if (VRegDef != RISCV::X0 &&  in doLocalPostpass()
1434     if (RISCV::isFaultFirstLoad(MI)) {  in insertReadVL()
1437         BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),  in insertReadVL()
1440       MI.getOperand(1).setReg(RISCV::X0);  in insertReadVL()
1518       if (MI.getOpcode() == RISCV::PseudoVSETVLI ||  in runOnMachineFunction()
1519           MI.getOpcode() == RISCV::PseudoVSETIVLI) {  in runOnMachineFunction()
1521         if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))  in runOnMachineFunction()
1522           MI.getOperand(0).setReg(RISCV::X0);  in runOnMachineFunction()