Home
last modified time | relevance | path

Searched refs:AMDGPU (Results 1 – 25 of 333) sorted by relevance

12345678910>>...14

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
200 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
443 if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass) in getLargestLegalSuperClass()
445 if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass) in getLargestLegalSuperClass()
450 if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass) in getLargestLegalSuperClass()
455 if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass) in getLargestLegalSuperClass()
460 if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass) in getLargestLegalSuperClass()
465 if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass) in getLargestLegalSuperClass()
1239 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0; in getFlatScratchSpillOpcode()
2933 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
[all …]
H A DAMDGPUCombinerHelper.cpp22 case AMDGPU::G_FADD: in fnegFoldsIntoMI()
23 case AMDGPU::G_FSUB: in fnegFoldsIntoMI()
24 case AMDGPU::G_FMUL: in fnegFoldsIntoMI()
25 case AMDGPU::G_FMA: in fnegFoldsIntoMI()
26 case AMDGPU::G_FMAD: in fnegFoldsIntoMI()
31 case AMDGPU::G_FSIN: in fnegFoldsIntoMI()
32 case AMDGPU::G_FPEXT: in fnegFoldsIntoMI()
35 case AMDGPU::G_FRINT: in fnegFoldsIntoMI()
81 case AMDGPU::COPY: in hasSourceMods()
83 case AMDGPU::G_FDIV: in hasSourceMods()
[all …]
H A DSIInstrInfo.cpp2806 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
2807 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, in insertSelect()
2808 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11, in insertSelect()
2809 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, in insertSelect()
2813 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3, in insertSelect()
2814 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7, in insertSelect()
2815 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11, in insertSelect()
2816 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15, in insertSelect()
4689 case AMDGPU::COPY: return AMDGPU::COPY; in getVALUOp()
4690 case AMDGPU::PHI: return AMDGPU::PHI; in getVALUOp()
[all …]
H A DAMDGPURegisterBankInfo.cpp118 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT || in applyBank()
340 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsic()
343 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsic()
352 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
355 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
358 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
361 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
402 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
405 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
775 AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term; in executeInWaterfallLoop()
[all …]
H A DAMDGPUResourceUsageAnalysis.cpp39 using namespace llvm::AMDGPU;
175 MRI.isPhysRegUsed(AMDGPU::VCC_LO) || MRI.isPhysRegUsed(AMDGPU::VCC_HI); in analyzeResourceUsage()
240 case AMDGPU::EXEC: in analyzeResourceUsage()
243 case AMDGPU::SCC: in analyzeResourceUsage()
244 case AMDGPU::M0: in analyzeResourceUsage()
253 case AMDGPU::MODE: in analyzeResourceUsage()
264 case AMDGPU::VCC: in analyzeResourceUsage()
265 case AMDGPU::VCC_LO: in analyzeResourceUsage()
266 case AMDGPU::VCC_HI: in analyzeResourceUsage()
287 case AMDGPU::TBA: in analyzeResourceUsage()
[all …]
H A DSILoadStoreOptimizer.cpp481 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
574 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
699 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
702 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
705 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in setMI()
711 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
1710 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1711 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
1712 {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5}, in getSubRegIdxs()
1713 {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6}, in getSubRegIdxs()
[all …]
H A DSIOptimizeExecMasking.cpp95 case AMDGPU::COPY: in isCopyFromExec()
96 case AMDGPU::S_MOV_B64: in isCopyFromExec()
98 case AMDGPU::S_MOV_B32: in isCopyFromExec()
112 case AMDGPU::COPY: in isCopyToExec()
133 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
149 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
173 case AMDGPU::S_OR_B64: in getSaveExecOp()
214 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
219 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
574 unsigned MovOpcode = IsSGPR32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVCMPSaveExecSequence()
[all …]
H A DGCNDPPCombine.cpp173 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
175 case AMDGPU::COPY: in getOldOpndValue()
238 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
312 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers)); in createDPPInst()
332 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::clamp) != -1) { in createDPPInst()
337 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::vdst_in) != -1) { in createDPPInst()
342 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::omod) != -1) { in createDPPInst()
355 if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel) != -1) in createDPPInst()
369 if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel_hi) != -1) in createDPPInst()
374 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_lo) != -1) { in createDPPInst()
[all …]
H A DAMDGPUSubtarget.cpp212 case AMDGPU::V_RCP_F16_e64: in zeroesHigh16BitsOfDest()
213 case AMDGPU::V_RCP_F16_e32: in zeroesHigh16BitsOfDest()
214 case AMDGPU::V_RSQ_F16_e64: in zeroesHigh16BitsOfDest()
215 case AMDGPU::V_RSQ_F16_e32: in zeroesHigh16BitsOfDest()
218 case AMDGPU::V_LOG_F16_e64: in zeroesHigh16BitsOfDest()
219 case AMDGPU::V_LOG_F16_e32: in zeroesHigh16BitsOfDest()
220 case AMDGPU::V_EXP_F16_e64: in zeroesHigh16BitsOfDest()
283 case AMDGPU::V_MADAK_F16: in zeroesHigh16BitsOfDest()
284 case AMDGPU::V_MADMK_F16: in zeroesHigh16BitsOfDest()
287 case AMDGPU::V_FMAMK_F16: in zeroesHigh16BitsOfDest()
[all …]
H A DSIPeepholeSDWA.cpp485 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
856 assert((Opc == AMDGPU::V_ADD_CO_U32_e64 || Opc == AMDGPU::V_SUB_CO_U32_e64) && in pseudoOpConvertToVOP2()
991 SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode)); in convertToSDWA()
1005 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst) != -1); in convertToSDWA()
1009 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1012 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1); in convertToSDWA()
1021 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0) != -1 && in convertToSDWA()
1033 AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1) != -1 && in convertToSDWA()
1053 assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::clamp) != -1); in convertToSDWA()
1062 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) { in convertToSDWA()
[all …]
H A DSIFoldOperands.cpp198 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) in updateOperand()
838 AMDGPU::getNamedOperandIdx(UseOpc, AMDGPU::OpName::src0))) { in foldOperand()
1013 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpc()
1059 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in tryConstantFoldOp()
1064 if ((Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 || in tryConstantFoldOp()
1072 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
1174 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in tryFoldCndMask()
1176 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in tryFoldCndMask()
1184 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in tryFoldCndMask()
1422 ((Op == AMDGPU::V_MUL_F64_e64 || Op == AMDGPU::V_MUL_F16_e64) && in isOMod()
[all …]
H A DSIShrinkInstructions.cpp91 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
216 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
221 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
240 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in shrinkMIMG()
257 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); in shrinkMIMG()
310 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
311 int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe); in shrinkMIMG()
342 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata), in shrinkMIMG()
723 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
736 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
[all …]
H A DAMDGPUInstructionSelector.cpp273 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32; in getLogicalBitOpcode()
275 return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32; in getLogicalBitOpcode()
277 return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32; in getLogicalBitOpcode()
431 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC) in selectG_UADDO_USUBO_UADDE_USUBE()
834 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectInterpP1F16()
1239 AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in selectGroupStaticSize()
1358 BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) in selectDSOrderedIntrinsic()
2130 AMDGPU::SReg_64RegClass : AMDGPU::SReg_32RegClass; in selectG_SZA_EXT()
2136 AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16; in selectG_SZA_EXT()
2234 &AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass; in selectG_CONSTANT()
[all …]
H A DAMDGPUArgumentUsageInfo.cpp100 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
117 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
120 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
124 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
134 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
138 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
158 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
166 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
167 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
168 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
[all …]
H A DGCNHazardRecognizer.cpp99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
143 case AMDGPU::S_SENDMSG: in isSendMsgTraceDataOrGDS()
148 case AMDGPU::DS_NOP: in isSendMsgTraceDataOrGDS()
1103 Opc != AMDGPU::V_NOP_e64 && Opc != AMDGPU::V_NOP_sdwa; in fixVcmpxPermlaneHazards()
1190 const AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(ST.getCPU()); in fixSMEMtoVectorWriteHazards()
1225 AMDGPU::Waitcnt Decoded = AMDGPU::decodeWaitcnt(IV, Imm); in fixSMEMtoVectorWriteHazards()
1250 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL) in fixSMEMtoVectorWriteHazards()
1755 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(I.getOpcode()); in checkNSAtoVMEMHazard()
1902 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards908()
2020 int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in checkMAIHazards90A()
[all …]
H A DSIInsertWaitcnts.cpp148 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); in getVmemType()
355 AMDGPU::IsaVersion IV;
542 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr); in updateByEvent()
619 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdst), in updateByEvent()
852 AMDGPU::Waitcnt OldWait = AMDGPU::decodeWaitcnt(IV, IEnc); in applyPreexistingWaitcnt()
942 return (Opc == AMDGPU::S_CBRANCH_VCCNZ || Opc == AMDGPU::S_CBRANCH_VCCZ) && in readsVCCZ()
982 AMDGPU::Waitcnt Wait; in generateWaitcntInstBefore()
1090 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in generateWaitcntInstBefore()
1102 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in generateWaitcntInstBefore()
1235 AMDGPU::Waitcnt Wait; in generateWaitcntBlockEnd()
[all …]
H A DSILateBranchLowering.cpp87 ? AMDGPU::Exp::ET_NULL in generateEndPgm()
88 : (HasColorExports ? AMDGPU::Exp::ET_MRT0 : AMDGPU::Exp::ET_MRTZ); in generateEndPgm()
91 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
92 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
93 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
94 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
141 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
142 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
151 case AMDGPU::S_BRANCH: in runOnMachineFunction()
161 case AMDGPU::SI_EARLY_TERMINATE_SCC0: in runOnMachineFunction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp27 case AMDGPU::S_WAITCNT: in postProcessInstruction()
28 case AMDGPU::S_WAITCNT_EXPCNT: in postProcessInstruction()
30 case AMDGPU::S_WAITCNT_VMCNT: in postProcessInstruction()
31 case AMDGPU::S_WAITCNT_VSCNT: in postProcessInstruction()
36 case AMDGPU::S_WAITCNT_gfx10: in postProcessInstruction()
38 case AMDGPU::S_WAITCNT_vi: in postProcessInstruction()
90 case AMDGPU::S_WAITCNT_vi: in checkCustomHazard()
176 AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU()); in computeWaitCnt()
239 AMDGPU::IsaVersion IV = AMDGPU::getIsaVersion(STI.getCPU()); in generateWaitCntInfo()
322 return Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::DS_GWS_INIT || in isAlwaysGDS()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/OpenMP/
H A Dcustom_state_machines.ll847 ; AMDGPU-NEXT: entry:
865 ; AMDGPU-NEXT: entry:
876 ; AMDGPU-NEXT: entry:
893 ; AMDGPU-NEXT: entry:
910 ; AMDGPU-NEXT: entry:
970 ; AMDGPU-NEXT: entry:
990 ; AMDGPU-NEXT: entry:
1000 ; AMDGPU-NEXT: entry:
1013 ; AMDGPU-NEXT: entry:
1023 ; AMDGPU-NEXT: entry:
[all …]
H A Dspmdization.ll197 ; AMDGPU-NEXT: entry:
359 ; AMDGPU-NEXT: entry:
458 ; AMDGPU-NEXT: entry:
489 ; AMDGPU-NEXT: entry:
542 ; AMDGPU-NEXT: entry:
704 ; AMDGPU-NEXT: entry:
820 ; AMDGPU-NEXT: entry:
851 ; AMDGPU-NEXT: entry:
905 ; AMDGPU-NEXT: entry:
1067 ; AMDGPU-NEXT: entry:
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp242 case AMDGPU::OPERAND_REG_IMM_FP32: in getLitEncoding()
255 case AMDGPU::OPERAND_REG_IMM_FP64: in getLitEncoding()
265 case AMDGPU::OPERAND_REG_IMM_FP16: in getLitEncoding()
289 case AMDGPU::OPERAND_KIMM32: in getLitEncoding()
290 case AMDGPU::OPERAND_KIMM16: in getLitEncoding()
299 using namespace AMDGPU::OpName; in getImplicitOpSelHiEncoding()
374 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); in encodeInstruction()
441 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
451 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { in getSDWASrcEncoding()
472 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
[all …]
H A DAMDGPUInstPrinter.cpp25 using namespace llvm::AMDGPU;
243 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
306 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
346 case AMDGPU::FP_REG: in printRegOperand()
347 case AMDGPU::SP_REG: in printRegOperand()
350 case AMDGPU::SCC: in printRegOperand()
419 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
803 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printRegularOperand()
1081 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1084 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2487 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2492 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2502 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2507 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2512 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
3606 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3612 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3693 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
4225 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
4452 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp308 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; in IsAGPROperand()
330 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeOperand_AVLdSt_Any()
699 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); in getInstruction()
823 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { in convertVOP3DPPInst()
851 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in convertMIMGInst()
978 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) in convertVOP3PDPPInst()
982 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) in convertVOP3PDPPInst()
990 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) in convertVOP3PDPPInst()
994 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) in convertVOP3PDPPInst()
1007 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) in convertVOPCDPPInst()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp103 namespace AMDGPU { namespace
969 if (AMDGPU::isGFX90A(*STI)) { in getDefaultAmdhsaKernelDescriptor()
1849 Reg == AMDGPU::SCC; in isSGPR()
1853 using namespace AMDGPU; \
1991 case AMDGPU::VS_32RegClassID: in getRegBitWidth()
1992 case AMDGPU::AV_32RegClassID: in getRegBitWidth()
1998 case AMDGPU::VS_64RegClassID: in getRegBitWidth()
2005 case AMDGPU::AV_64RegClassID: in getRegBitWidth()
2014 case AMDGPU::AV_96RegClassID: in getRegBitWidth()
2023 case AMDGPU::AV_128RegClassID: in getRegBitWidth()
[all …]

12345678910>>...14