Lines Matching refs:AMDGPU
43 using namespace llvm::AMDGPU;
264 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrImmWithInt16InputMods()
268 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrImmWithInt32InputMods()
272 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrInlineImmWithInt16InputMods()
276 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrInlineImmWithInt32InputMods()
280 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); in isRegOrImmWithInt64InputMods()
284 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrImmWithFP16InputMods()
288 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrImmWithFP32InputMods()
292 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); in isRegOrImmWithFP64InputMods()
296 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrInlineImmWithFP16InputMods()
300 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrInlineImmWithFP32InputMods()
305 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVReg()
306 isRegClass(AMDGPU::VReg_64RegClassID) || in isVReg()
307 isRegClass(AMDGPU::VReg_96RegClassID) || in isVReg()
308 isRegClass(AMDGPU::VReg_128RegClassID) || in isVReg()
309 isRegClass(AMDGPU::VReg_160RegClassID) || in isVReg()
310 isRegClass(AMDGPU::VReg_192RegClassID) || in isVReg()
311 isRegClass(AMDGPU::VReg_256RegClassID) || in isVReg()
312 isRegClass(AMDGPU::VReg_512RegClassID) || in isVReg()
313 isRegClass(AMDGPU::VReg_1024RegClassID); in isVReg()
317 return isRegClass(AMDGPU::VGPR_32RegClassID); in isVReg32()
325 return isRegKind() && getReg() == AMDGPU::SGPR_NULL; in isNull()
406 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); in isSCSrcB16()
414 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); in isSCSrcB32()
418 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); in isSCSrcB64()
424 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); in isSCSrcF16()
432 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); in isSCSrcF32()
436 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); in isSCSrcF64()
496 return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) || in isSSrcOrLdsB32()
501 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); in isVCSrcB32()
505 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); in isVCSrcB64()
509 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); in isVCSrcB16()
517 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); in isVCSrcF32()
521 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); in isVCSrcF64()
525 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); in isVCSrcF16()
581 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32); in isVISrcB32()
585 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16); in isVISrcB16()
593 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32); in isVISrcF32()
597 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); in isVISrcF16()
605 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64); in isVISrc_64B64()
609 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64); in isVISrc_64F64()
613 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32); in isVISrc_64V2FP32()
617 return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32); in isVISrc_64V2INT32()
621 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64); in isVISrc_256B64()
625 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64); in isVISrc_256F64()
629 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16); in isVISrc_128B16()
637 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32); in isVISrc_128B32()
641 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32); in isVISrc_128F32()
645 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32); in isVISrc_256V2FP32()
649 return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32); in isVISrc_256V2INT32()
653 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32); in isVISrc_512B32()
657 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16); in isVISrc_512B16()
665 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32); in isVISrc_512F32()
669 return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16); in isVISrc_512F16()
677 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32); in isVISrc_1024B32()
681 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16); in isVISrc_1024B16()
689 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32); in isVISrc_1024F32()
693 return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16); in isVISrc_1024F16()
701 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32); in isAISrcB32()
705 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16); in isAISrcB16()
713 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32); in isAISrcF32()
717 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); in isAISrcF16()
725 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64); in isAISrc_64B64()
729 return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64); in isAISrc_64F64()
733 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32); in isAISrc_128B32()
737 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16); in isAISrc_128B16()
745 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32); in isAISrc_128F32()
749 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); in isAISrc_128F16()
757 return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16); in isVISrc_128F16()
765 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64); in isAISrc_256B64()
769 return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64); in isAISrc_256F64()
773 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32); in isAISrc_512B32()
777 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16); in isAISrc_512B16()
785 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32); in isAISrc_512F32()
789 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); in isAISrc_512F16()
797 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32); in isAISrc_1024B32()
801 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16); in isAISrc_1024B16()
809 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32); in isAISrc_1024F32()
813 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); in isAISrc_1024F16()
1367 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
1395 return AMDGPU::hasMIMG_R128(getSTI()); in hasMIMG_R128()
1399 return AMDGPU::hasPackedD16(getSTI()); in hasPackedD16()
1403 return AMDGPU::hasGFX10A16(getSTI()); in hasGFX10A16()
1406 bool hasG16() const { return AMDGPU::hasG16(getSTI()); } in hasG16()
1409 return AMDGPU::isSI(getSTI()); in isSI()
1413 return AMDGPU::isCI(getSTI()); in isCI()
1417 return AMDGPU::isVI(getSTI()); in isVI()
1421 return AMDGPU::isGFX9(getSTI()); in isGFX9()
1426 return AMDGPU::isGFX90A(getSTI()); in isGFX90A()
1430 return AMDGPU::isGFX940(getSTI()); in isGFX940()
1434 return AMDGPU::isGFX9Plus(getSTI()); in isGFX9Plus()
1438 return AMDGPU::isGFX10(getSTI()); in isGFX10()
1441 bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } in isGFX10Plus()
1444 return AMDGPU::isGFX11(getSTI()); in isGFX11()
1448 return AMDGPU::isGFX11Plus(getSTI()); in isGFX11Plus()
1452 return AMDGPU::isGFX10_BEncoding(getSTI()); in isGFX10_BEncoding()
1456 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; in hasInv2PiInlineImm()
1460 return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; in hasFlatOffsets()
1464 return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; in hasArchitectedFlatScratch()
1474 return getFeatureBits()[AMDGPU::FeatureIntClamp]; in hasIntClamp()
1832 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1833 case AMDGPU::OPERAND_REG_IMM_FP32: in getOpFltSemantics()
1834 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in getOpFltSemantics()
1835 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getOpFltSemantics()
1836 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getOpFltSemantics()
1837 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in getOpFltSemantics()
1838 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in getOpFltSemantics()
1839 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in getOpFltSemantics()
1840 case AMDGPU::OPERAND_REG_IMM_V2FP32: in getOpFltSemantics()
1841 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in getOpFltSemantics()
1842 case AMDGPU::OPERAND_REG_IMM_V2INT32: in getOpFltSemantics()
1843 case AMDGPU::OPERAND_KIMM32: in getOpFltSemantics()
1845 case AMDGPU::OPERAND_REG_IMM_INT64: in getOpFltSemantics()
1846 case AMDGPU::OPERAND_REG_IMM_FP64: in getOpFltSemantics()
1847 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in getOpFltSemantics()
1848 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in getOpFltSemantics()
1849 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in getOpFltSemantics()
1851 case AMDGPU::OPERAND_REG_IMM_INT16: in getOpFltSemantics()
1852 case AMDGPU::OPERAND_REG_IMM_FP16: in getOpFltSemantics()
1853 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in getOpFltSemantics()
1854 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in getOpFltSemantics()
1855 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in getOpFltSemantics()
1856 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in getOpFltSemantics()
1857 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in getOpFltSemantics()
1858 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in getOpFltSemantics()
1859 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in getOpFltSemantics()
1860 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in getOpFltSemantics()
1861 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in getOpFltSemantics()
1862 case AMDGPU::OPERAND_REG_IMM_V2INT16: in getOpFltSemantics()
1863 case AMDGPU::OPERAND_REG_IMM_V2FP16: in getOpFltSemantics()
1864 case AMDGPU::OPERAND_KIMM16: in getOpFltSemantics()
1904 return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi); in isInlineableLiteralOp16()
1929 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1944 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1951 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1965 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
2023 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVRegWithInputMods()
2025 (isRegClass(AMDGPU::VReg_64RegClassID) && in isVRegWithInputMods()
2026 AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]); in isVRegWithInputMods()
2033 return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); in isSDWAOperand()
2056 return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || in isBoolReg()
2057 (FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32())); in isBoolReg()
2078 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
2094 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2097 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2107 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
2108 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
2109 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
2110 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
2111 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
2112 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), in addLiteralImmOperand()
2120 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
2138 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2139 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2140 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in addLiteralImmOperand()
2141 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2142 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2143 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2144 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2145 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2146 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2147 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in addLiteralImmOperand()
2148 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2149 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2150 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2151 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2152 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2153 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2154 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2155 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in addLiteralImmOperand()
2156 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2157 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2158 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2159 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2160 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2161 case AMDGPU::OPERAND_REG_IMM_V2INT32: in addLiteralImmOperand()
2162 case AMDGPU::OPERAND_KIMM32: in addLiteralImmOperand()
2163 case AMDGPU::OPERAND_KIMM16: { in addLiteralImmOperand()
2187 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
2188 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
2189 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in addLiteralImmOperand()
2190 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
2191 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
2192 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
2193 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
2194 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
2195 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
2196 case AMDGPU::OPERAND_REG_IMM_V2FP32: in addLiteralImmOperand()
2197 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in addLiteralImmOperand()
2198 case AMDGPU::OPERAND_REG_IMM_V2INT32: in addLiteralImmOperand()
2199 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in addLiteralImmOperand()
2201 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), in addLiteralImmOperand()
2212 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
2213 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
2214 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
2215 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
2216 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in addLiteralImmOperand()
2217 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
2227 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
2228 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
2229 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in addLiteralImmOperand()
2230 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
2231 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
2232 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
2233 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
2235 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2246 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
2247 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
2248 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
2249 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { in addLiteralImmOperand()
2251 assert(AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
2257 case AMDGPU::OPERAND_KIMM32: in addLiteralImmOperand()
2261 case AMDGPU::OPERAND_KIMM16: in addLiteralImmOperand()
2289 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
2294 case AMDGPU::SRC_SHARED_BASE: in isInlineValue()
2295 case AMDGPU::SRC_SHARED_LIMIT: in isInlineValue()
2296 case AMDGPU::SRC_PRIVATE_BASE: in isInlineValue()
2297 case AMDGPU::SRC_PRIVATE_LIMIT: in isInlineValue()
2298 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in isInlineValue()
2300 case AMDGPU::SRC_VCCZ: in isInlineValue()
2301 case AMDGPU::SRC_EXECZ: in isInlineValue()
2302 case AMDGPU::SRC_SCC: in isInlineValue()
2304 case AMDGPU::SGPR_NULL: in isInlineValue()
2324 return AMDGPU::VGPR_32RegClassID; in getRegClass()
2326 return AMDGPU::VReg_64RegClassID; in getRegClass()
2328 return AMDGPU::VReg_96RegClassID; in getRegClass()
2330 return AMDGPU::VReg_128RegClassID; in getRegClass()
2332 return AMDGPU::VReg_160RegClassID; in getRegClass()
2334 return AMDGPU::VReg_192RegClassID; in getRegClass()
2336 return AMDGPU::VReg_224RegClassID; in getRegClass()
2338 return AMDGPU::VReg_256RegClassID; in getRegClass()
2340 return AMDGPU::VReg_512RegClassID; in getRegClass()
2342 return AMDGPU::VReg_1024RegClassID; in getRegClass()
2348 return AMDGPU::TTMP_32RegClassID; in getRegClass()
2350 return AMDGPU::TTMP_64RegClassID; in getRegClass()
2352 return AMDGPU::TTMP_128RegClassID; in getRegClass()
2354 return AMDGPU::TTMP_256RegClassID; in getRegClass()
2356 return AMDGPU::TTMP_512RegClassID; in getRegClass()
2362 return AMDGPU::SGPR_32RegClassID; in getRegClass()
2364 return AMDGPU::SGPR_64RegClassID; in getRegClass()
2366 return AMDGPU::SGPR_96RegClassID; in getRegClass()
2368 return AMDGPU::SGPR_128RegClassID; in getRegClass()
2370 return AMDGPU::SGPR_160RegClassID; in getRegClass()
2372 return AMDGPU::SGPR_192RegClassID; in getRegClass()
2374 return AMDGPU::SGPR_224RegClassID; in getRegClass()
2376 return AMDGPU::SGPR_256RegClassID; in getRegClass()
2378 return AMDGPU::SGPR_512RegClassID; in getRegClass()
2384 return AMDGPU::AGPR_32RegClassID; in getRegClass()
2386 return AMDGPU::AReg_64RegClassID; in getRegClass()
2388 return AMDGPU::AReg_96RegClassID; in getRegClass()
2390 return AMDGPU::AReg_128RegClassID; in getRegClass()
2392 return AMDGPU::AReg_160RegClassID; in getRegClass()
2394 return AMDGPU::AReg_192RegClassID; in getRegClass()
2396 return AMDGPU::AReg_224RegClassID; in getRegClass()
2398 return AMDGPU::AReg_256RegClassID; in getRegClass()
2400 return AMDGPU::AReg_512RegClassID; in getRegClass()
2402 return AMDGPU::AReg_1024RegClassID; in getRegClass()
2410 .Case("exec", AMDGPU::EXEC) in getSpecialRegForName()
2411 .Case("vcc", AMDGPU::VCC) in getSpecialRegForName()
2412 .Case("flat_scratch", AMDGPU::FLAT_SCR) in getSpecialRegForName()
2413 .Case("xnack_mask", AMDGPU::XNACK_MASK) in getSpecialRegForName()
2414 .Case("shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2415 .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2416 .Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2417 .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2418 .Case("private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2419 .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2420 .Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2421 .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2422 .Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2423 .Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2424 .Case("lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2425 .Case("src_lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2426 .Case("m0", AMDGPU::M0) in getSpecialRegForName()
2427 .Case("vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2428 .Case("src_vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2429 .Case("execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2430 .Case("src_execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2431 .Case("scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2432 .Case("src_scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2433 .Case("tba", AMDGPU::TBA) in getSpecialRegForName()
2434 .Case("tma", AMDGPU::TMA) in getSpecialRegForName()
2435 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) in getSpecialRegForName()
2436 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) in getSpecialRegForName()
2437 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) in getSpecialRegForName()
2438 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) in getSpecialRegForName()
2439 .Case("vcc_lo", AMDGPU::VCC_LO) in getSpecialRegForName()
2440 .Case("vcc_hi", AMDGPU::VCC_HI) in getSpecialRegForName()
2441 .Case("exec_lo", AMDGPU::EXEC_LO) in getSpecialRegForName()
2442 .Case("exec_hi", AMDGPU::EXEC_HI) in getSpecialRegForName()
2443 .Case("tma_lo", AMDGPU::TMA_LO) in getSpecialRegForName()
2444 .Case("tma_hi", AMDGPU::TMA_HI) in getSpecialRegForName()
2445 .Case("tba_lo", AMDGPU::TBA_LO) in getSpecialRegForName()
2446 .Case("tba_hi", AMDGPU::TBA_HI) in getSpecialRegForName()
2447 .Case("pc", AMDGPU::PC_REG) in getSpecialRegForName()
2448 .Case("null", AMDGPU::SGPR_NULL) in getSpecialRegForName()
2449 .Default(AMDGPU::NoRegister); in getSpecialRegForName()
2487 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2488 Reg = AMDGPU::EXEC; in AddNextRegisterToList()
2492 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2493 Reg = AMDGPU::FLAT_SCR; in AddNextRegisterToList()
2497 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { in AddNextRegisterToList()
2498 Reg = AMDGPU::XNACK_MASK; in AddNextRegisterToList()
2502 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2503 Reg = AMDGPU::VCC; in AddNextRegisterToList()
2507 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2508 Reg = AMDGPU::TBA; in AddNextRegisterToList()
2512 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
2513 Reg = AMDGPU::TMA; in AddNextRegisterToList()
2595 return getSpecialRegForName(Str) != AMDGPU::NoRegister; in isRegister()
2621 return AMDGPU::NoRegister; in getRegularReg()
2628 return AMDGPU::NoRegister; in getRegularReg()
2635 return AMDGPU::NoRegister; in getRegularReg()
2708 return AMDGPU::NoRegister; in ParseRegularReg()
2720 return AMDGPU::NoRegister; in ParseRegularReg()
2726 return AMDGPU::NoRegister; in ParseRegularReg()
2735 unsigned Reg = AMDGPU::NoRegister; in ParseRegList()
2740 return AMDGPU::NoRegister; in ParseRegList()
2747 return AMDGPU::NoRegister; in ParseRegList()
2750 return AMDGPU::NoRegister; in ParseRegList()
2761 return AMDGPU::NoRegister; in ParseRegList()
2765 return AMDGPU::NoRegister; in ParseRegList()
2769 return AMDGPU::NoRegister; in ParseRegList()
2772 return AMDGPU::NoRegister; in ParseRegList()
2777 return AMDGPU::NoRegister; in ParseRegList()
2790 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2794 if (Reg == AMDGPU::NoRegister) in ParseAMDGPURegister()
2801 if (Reg == AMDGPU::NoRegister) { in ParseAMDGPURegister()
2807 if (Reg == AMDGPU::SGPR_NULL) { in ParseAMDGPURegister()
2821 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2858 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
3239 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in checkTargetMatchPredicate()
3240 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in checkTargetMatchPredicate()
3243 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3245 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
3318 case AMDGPU::FLAT_SCR: in findImplicitSGPRReadInVOP()
3319 case AMDGPU::VCC: in findImplicitSGPRReadInVOP()
3320 case AMDGPU::VCC_LO: in findImplicitSGPRReadInVOP()
3321 case AMDGPU::VCC_HI: in findImplicitSGPRReadInVOP()
3322 case AMDGPU::M0: in findImplicitSGPRReadInVOP()
3328 return AMDGPU::NoRegister; in findImplicitSGPRReadInVOP()
3339 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) { in isInlineConstant()
3346 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant()
3350 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm()); in isInlineConstant()
3352 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm()); in isInlineConstant()
3355 if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 || in isInlineConstant()
3356 OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 || in isInlineConstant()
3357 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16) in isInlineConstant()
3358 return AMDGPU::isInlinableIntLiteral(Val); in isInlineConstant()
3360 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in isInlineConstant()
3361 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 || in isInlineConstant()
3362 OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16) in isInlineConstant()
3363 return AMDGPU::isInlinableIntLiteralV216(Val); in isInlineConstant()
3365 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 || in isInlineConstant()
3366 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 || in isInlineConstant()
3367 OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) in isInlineConstant()
3368 return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm()); in isInlineConstant()
3370 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm()); in isInlineConstant()
3383 case AMDGPU::V_LSHLREV_B64_e64: in getConstantBusLimit()
3384 case AMDGPU::V_LSHLREV_B64_gfx10: in getConstantBusLimit()
3385 case AMDGPU::V_LSHLREV_B64_e64_gfx11: in getConstantBusLimit()
3386 case AMDGPU::V_LSHRREV_B64_e64: in getConstantBusLimit()
3387 case AMDGPU::V_LSHRREV_B64_gfx10: in getConstantBusLimit()
3388 case AMDGPU::V_LSHRREV_B64_e64_gfx11: in getConstantBusLimit()
3389 case AMDGPU::V_ASHRREV_I64_e64: in getConstantBusLimit()
3390 case AMDGPU::V_ASHRREV_I64_gfx10: in getConstantBusLimit()
3391 case AMDGPU::V_ASHRREV_I64_e64_gfx11: in getConstantBusLimit()
3392 case AMDGPU::V_LSHL_B64_e64: in getConstantBusLimit()
3393 case AMDGPU::V_LSHR_B64_e64: in getConstantBusLimit()
3394 case AMDGPU::V_ASHR_I64_e64: in getConstantBusLimit()
3420 unsigned LastSGPR = AMDGPU::NoRegister; in validateConstantBusLimitations()
3431 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { in validateConstantBusLimitations()
3438 if (SGPRUsed != AMDGPU::NoRegister) { in validateConstantBusLimitations()
3443 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateConstantBusLimitations()
3444 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
3445 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateConstantBusLimitations()
3479 unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx); in validateConstantBusLimitations()
3510 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()
3518 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateEarlyClobberLimitations()
3519 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
3520 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateEarlyClobberLimitations()
3550 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
3566 int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); in validateMIMGDataSize()
3567 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
3568 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
3575 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
3585 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGDataSize()
3606 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3608 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGAddrSize()
3609 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGAddrSize()
3610 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize()
3611 int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in validateMIMGAddrSize()
3612 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3613 int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16); in validateMIMGAddrSize()
3623 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGAddrSize()
3627 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()
3631 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16()); in validateMIMGAddrSize()
3657 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
3675 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
3693 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGMSAA()
3694 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGMSAA()
3695 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGMSAA()
3700 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGMSAA()
3704 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGMSAA()
3712 case AMDGPU::V_MOVRELS_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3713 case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3714 case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3733 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMovrels()
3757 if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi) in validateMAIAccWrite()
3760 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMAIAccWrite()
3786 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); in validateMFMA()
3827 for (auto Name : {AMDGPU::OpName::src0_modifiers, in validateDivScale()
3828 AMDGPU::OpName::src2_modifiers, in validateDivScale()
3829 AMDGPU::OpName::src2_modifiers}) { in validateDivScale()
3830 if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name)) in validateDivScale()
3848 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
3864 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGDim()
3878 case AMDGPU::V_SUBREV_F32_e32: in IsRevOpcode()
3879 case AMDGPU::V_SUBREV_F32_e64: in IsRevOpcode()
3880 case AMDGPU::V_SUBREV_F32_e32_gfx10: in IsRevOpcode()
3881 case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7: in IsRevOpcode()
3882 case AMDGPU::V_SUBREV_F32_e32_vi: in IsRevOpcode()
3883 case AMDGPU::V_SUBREV_F32_e64_gfx10: in IsRevOpcode()
3884 case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7: in IsRevOpcode()
3885 case AMDGPU::V_SUBREV_F32_e64_vi: in IsRevOpcode()
3887 case AMDGPU::V_SUBREV_CO_U32_e32: in IsRevOpcode()
3888 case AMDGPU::V_SUBREV_CO_U32_e64: in IsRevOpcode()
3889 case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3890 case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3892 case AMDGPU::V_SUBBREV_U32_e32: in IsRevOpcode()
3893 case AMDGPU::V_SUBBREV_U32_e64: in IsRevOpcode()
3894 case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7: in IsRevOpcode()
3895 case AMDGPU::V_SUBBREV_U32_e32_vi: in IsRevOpcode()
3896 case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7: in IsRevOpcode()
3897 case AMDGPU::V_SUBBREV_U32_e64_vi: in IsRevOpcode()
3899 case AMDGPU::V_SUBREV_U32_e32: in IsRevOpcode()
3900 case AMDGPU::V_SUBREV_U32_e64: in IsRevOpcode()
3901 case AMDGPU::V_SUBREV_U32_e32_gfx9: in IsRevOpcode()
3902 case AMDGPU::V_SUBREV_U32_e32_vi: in IsRevOpcode()
3903 case AMDGPU::V_SUBREV_U32_e64_gfx9: in IsRevOpcode()
3904 case AMDGPU::V_SUBREV_U32_e64_vi: in IsRevOpcode()
3906 case AMDGPU::V_SUBREV_F16_e32: in IsRevOpcode()
3907 case AMDGPU::V_SUBREV_F16_e64: in IsRevOpcode()
3908 case AMDGPU::V_SUBREV_F16_e32_gfx10: in IsRevOpcode()
3909 case AMDGPU::V_SUBREV_F16_e32_vi: in IsRevOpcode()
3910 case AMDGPU::V_SUBREV_F16_e64_gfx10: in IsRevOpcode()
3911 case AMDGPU::V_SUBREV_F16_e64_vi: in IsRevOpcode()
3913 case AMDGPU::V_SUBREV_U16_e32: in IsRevOpcode()
3914 case AMDGPU::V_SUBREV_U16_e64: in IsRevOpcode()
3915 case AMDGPU::V_SUBREV_U16_e32_vi: in IsRevOpcode()
3916 case AMDGPU::V_SUBREV_U16_e64_vi: in IsRevOpcode()
3918 case AMDGPU::V_SUBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3919 case AMDGPU::V_SUBREV_CO_U32_e64_gfx10: in IsRevOpcode()
3920 case AMDGPU::V_SUBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3922 case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3923 case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3925 case AMDGPU::V_SUBREV_NC_U32_e32_gfx10: in IsRevOpcode()
3926 case AMDGPU::V_SUBREV_NC_U32_e64_gfx10: in IsRevOpcode()
3928 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in IsRevOpcode()
3929 case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10: in IsRevOpcode()
3931 case AMDGPU::V_LSHRREV_B32_e32: in IsRevOpcode()
3932 case AMDGPU::V_LSHRREV_B32_e64: in IsRevOpcode()
3933 case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3934 case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3935 case AMDGPU::V_LSHRREV_B32_e32_vi: in IsRevOpcode()
3936 case AMDGPU::V_LSHRREV_B32_e64_vi: in IsRevOpcode()
3937 case AMDGPU::V_LSHRREV_B32_e32_gfx10: in IsRevOpcode()
3938 case AMDGPU::V_LSHRREV_B32_e64_gfx10: in IsRevOpcode()
3940 case AMDGPU::V_ASHRREV_I32_e32: in IsRevOpcode()
3941 case AMDGPU::V_ASHRREV_I32_e64: in IsRevOpcode()
3942 case AMDGPU::V_ASHRREV_I32_e32_gfx10: in IsRevOpcode()
3943 case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3944 case AMDGPU::V_ASHRREV_I32_e32_vi: in IsRevOpcode()
3945 case AMDGPU::V_ASHRREV_I32_e64_gfx10: in IsRevOpcode()
3946 case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3947 case AMDGPU::V_ASHRREV_I32_e64_vi: in IsRevOpcode()
3949 case AMDGPU::V_LSHLREV_B32_e32: in IsRevOpcode()
3950 case AMDGPU::V_LSHLREV_B32_e64: in IsRevOpcode()
3951 case AMDGPU::V_LSHLREV_B32_e32_gfx10: in IsRevOpcode()
3952 case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3953 case AMDGPU::V_LSHLREV_B32_e32_vi: in IsRevOpcode()
3954 case AMDGPU::V_LSHLREV_B32_e64_gfx10: in IsRevOpcode()
3955 case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3956 case AMDGPU::V_LSHLREV_B32_e64_vi: in IsRevOpcode()
3958 case AMDGPU::V_LSHLREV_B16_e32: in IsRevOpcode()
3959 case AMDGPU::V_LSHLREV_B16_e64: in IsRevOpcode()
3960 case AMDGPU::V_LSHLREV_B16_e32_vi: in IsRevOpcode()
3961 case AMDGPU::V_LSHLREV_B16_e64_vi: in IsRevOpcode()
3962 case AMDGPU::V_LSHLREV_B16_gfx10: in IsRevOpcode()
3964 case AMDGPU::V_LSHRREV_B16_e32: in IsRevOpcode()
3965 case AMDGPU::V_LSHRREV_B16_e64: in IsRevOpcode()
3966 case AMDGPU::V_LSHRREV_B16_e32_vi: in IsRevOpcode()
3967 case AMDGPU::V_LSHRREV_B16_e64_vi: in IsRevOpcode()
3968 case AMDGPU::V_LSHRREV_B16_gfx10: in IsRevOpcode()
3970 case AMDGPU::V_ASHRREV_I16_e32: in IsRevOpcode()
3971 case AMDGPU::V_ASHRREV_I16_e64: in IsRevOpcode()
3972 case AMDGPU::V_ASHRREV_I16_e32_vi: in IsRevOpcode()
3973 case AMDGPU::V_ASHRREV_I16_e64_vi: in IsRevOpcode()
3974 case AMDGPU::V_ASHRREV_I16_gfx10: in IsRevOpcode()
3976 case AMDGPU::V_LSHLREV_B64_e64: in IsRevOpcode()
3977 case AMDGPU::V_LSHLREV_B64_gfx10: in IsRevOpcode()
3978 case AMDGPU::V_LSHLREV_B64_vi: in IsRevOpcode()
3980 case AMDGPU::V_LSHRREV_B64_e64: in IsRevOpcode()
3981 case AMDGPU::V_LSHRREV_B64_gfx10: in IsRevOpcode()
3982 case AMDGPU::V_LSHRREV_B64_vi: in IsRevOpcode()
3984 case AMDGPU::V_ASHRREV_I64_e64: in IsRevOpcode()
3985 case AMDGPU::V_ASHRREV_I64_gfx10: in IsRevOpcode()
3986 case AMDGPU::V_ASHRREV_I64_vi: in IsRevOpcode()
3988 case AMDGPU::V_PK_LSHLREV_B16: in IsRevOpcode()
3989 case AMDGPU::V_PK_LSHLREV_B16_gfx10: in IsRevOpcode()
3990 case AMDGPU::V_PK_LSHLREV_B16_vi: in IsRevOpcode()
3992 case AMDGPU::V_PK_LSHRREV_B16: in IsRevOpcode()
3993 case AMDGPU::V_PK_LSHRREV_B16_gfx10: in IsRevOpcode()
3994 case AMDGPU::V_PK_LSHRREV_B16_vi: in IsRevOpcode()
3995 case AMDGPU::V_PK_ASHRREV_I16: in IsRevOpcode()
3996 case AMDGPU::V_PK_ASHRREV_I16_gfx10: in IsRevOpcode()
3997 case AMDGPU::V_PK_ASHRREV_I16_vi: in IsRevOpcode()
4053 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateFlatOffset()
4066 unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), true); in validateFlatOffset()
4073 unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), false); in validateFlatOffset()
4104 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateSMEMOffset()
4113 bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode); in validateSMEMOffset()
4114 if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) || in validateSMEMOffset()
4115 AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer)) in validateSMEMOffset()
4131 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateSOPLiteral()
4132 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateSOPLiteral()
4145 if (AMDGPU::isSISrcOperand(Desc, OpIdx)) { in validateSOPLiteral()
4163 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || in validateOpSel()
4164 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { in validateOpSel()
4165 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4175 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4180 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in validateOpSel()
4190 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
4202 int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl); in validateDPP()
4207 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) { in validateDPP()
4209 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateDPP()
4211 getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) { in validateDPP()
4224 return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) || in validateVccOperand()
4225 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
4233 const int ImmIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm); in validateVOPLiteral()
4238 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateVOPLiteral()
4239 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateVOPLiteral()
4240 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateVOPLiteral()
4255 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) in validateVOPLiteral()
4259 getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) { in validateVOPLiteral()
4280 if (ImmIdx == -1 && !getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in validateVOPLiteral()
4296 int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx); in IsAGPROperand()
4304 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
4306 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in IsAGPROperand()
4317 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in validateAGPRLdSt()
4318 : AMDGPU::OpName::vdata; in validateAGPRLdSt()
4321 int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI); in validateAGPRLdSt()
4325 int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI); in validateAGPRLdSt()
4331 if (FB[AMDGPU::FeatureGFX90AInsts]) { in validateAGPRLdSt()
4342 if (!FB[AMDGPU::FeatureGFX90AInsts]) in validateVGPRAlign()
4346 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateVGPRAlign()
4347 const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); in validateVGPRAlign()
4353 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in validateVGPRAlign()
4357 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4359 if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) in validateVGPRAlign()
4378 int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp); in validateBLGP()
4387 if (FB[AMDGPU::FeatureGFX940Insts]) { in validateBLGP()
4389 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: in validateBLGP()
4390 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: in validateBLGP()
4391 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: in validateBLGP()
4392 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: in validateBLGP()
4411 if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) in validateGWS()
4415 if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi && in validateGWS()
4416 Opc != AMDGPU::DS_GWS_SEMA_BR_vi) in validateGWS()
4420 const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); in validateGWS()
4422 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); in validateGWS()
4425 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()
4438 int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in validateCoherencyBits()
4439 AMDGPU::OpName::cpol); in validateCoherencyBits()
4452 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4619 Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts] in validateInstruction()
5257 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in ParseDirectiveHSACodeObjectISA()
5310 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
5313 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
5322 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
5325 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
5353 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI()); in ParseDirectiveAMDKernelCodeT()
5479 if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin, in ParseDirectivePALMetadataBegin()
5480 AMDGPU::PALMD::AssemblerDirectiveEnd, String)) in ParseDirectivePALMetadataBegin()
5535 unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); in ParseDirectiveAMDGPULDS()
5580 if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) in ParseDirective()
5598 if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) in ParseDirective()
5620 if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo)) in subtargetHasRegister()
5624 if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo)) in subtargetHasRegister()
5628 case AMDGPU::SRC_SHARED_BASE: in subtargetHasRegister()
5629 case AMDGPU::SRC_SHARED_LIMIT: in subtargetHasRegister()
5630 case AMDGPU::SRC_PRIVATE_BASE: in subtargetHasRegister()
5631 case AMDGPU::SRC_PRIVATE_LIMIT: in subtargetHasRegister()
5633 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in subtargetHasRegister()
5635 case AMDGPU::TBA: in subtargetHasRegister()
5636 case AMDGPU::TBA_LO: in subtargetHasRegister()
5637 case AMDGPU::TBA_HI: in subtargetHasRegister()
5638 case AMDGPU::TMA: in subtargetHasRegister()
5639 case AMDGPU::TMA_LO: in subtargetHasRegister()
5640 case AMDGPU::TMA_HI: in subtargetHasRegister()
5642 case AMDGPU::XNACK_MASK: in subtargetHasRegister()
5643 case AMDGPU::XNACK_MASK_LO: in subtargetHasRegister()
5644 case AMDGPU::XNACK_MASK_HI: in subtargetHasRegister()
5646 case AMDGPU::SGPR_NULL: in subtargetHasRegister()
5660 case AMDGPU::FLAT_SCR: in subtargetHasRegister()
5661 case AMDGPU::FLAT_SCR_LO: in subtargetHasRegister()
5662 case AMDGPU::FLAT_SCR_HI: in subtargetHasRegister()
5671 if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo)) in subtargetHasRegister()
5923 CPolOn = AMDGPU::CPol::SC0; in parseCPol()
5925 CPolOff = AMDGPU::CPol::SC0; in parseCPol()
5927 CPolOn = AMDGPU::CPol::NT; in parseCPol()
5929 CPolOff = AMDGPU::CPol::NT; in parseCPol()
5931 CPolOn = AMDGPU::CPol::SC1; in parseCPol()
5933 CPolOff = AMDGPU::CPol::SC1; in parseCPol()
5938 CPolOn = AMDGPU::CPol::GLC; in parseCPol()
5940 CPolOff = AMDGPU::CPol::GLC; in parseCPol()
5942 CPolOn = AMDGPU::CPol::SLC; in parseCPol()
5944 CPolOff = AMDGPU::CPol::SLC; in parseCPol()
5946 CPolOn = AMDGPU::CPol::DLC; in parseCPol()
5948 CPolOff = AMDGPU::CPol::DLC; in parseCPol()
5950 CPolOn = AMDGPU::CPol::SCC; in parseCPol()
5952 CPolOff = AMDGPU::CPol::SCC; in parseCPol()
5956 if (!isGFX10Plus() && ((CPolOn | CPolOff) & AMDGPU::CPol::DLC)) { in parseCPol()
5961 if (!isGFX90A() && ((CPolOn | CPolOff) & AMDGPU::CPol::SCC)) { in parseCPol()
6042 using namespace llvm::AMDGPU::MTBUFFormat; in parseDfmtNfmt()
6075 using namespace llvm::AMDGPU::MTBUFFormat; in parseUfmt()
6093 using namespace llvm::AMDGPU::MTBUFFormat; in matchDfmtNfmt()
6116 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicSplitFormat()
6160 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicUnifiedFormat()
6177 using namespace llvm::AMDGPU::MTBUFFormat; in parseNumericFormat()
6192 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicOrNumericFormat()
6220 using namespace llvm::AMDGPU::MTBUFFormat; in parseFORMAT()
6297 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSOffset01()
6331 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSImpl()
6356 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister)); in cvtExp()
6379 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
6380 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
6384 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
6401 const AMDGPU::IsaVersion ISA, in encodeCnt()
6435 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
6471 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
6603 using namespace llvm::AMDGPU::DepCtr; in parseDepCtr()
6640 using namespace llvm::AMDGPU::DepCtr; in parseDepCtrOps()
6670 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()
6706 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()
6735 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()
6775 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgBody()
6811 using namespace llvm::AMDGPU::SendMsg; in validateSendMsg()
6855 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgOp()
6965 using namespace llvm::AMDGPU::Exp; in parseExpTgt()
7208 using namespace llvm::AMDGPU::Swizzle; in encodeBitmaskPerm()
7253 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleQuadPerm()
7269 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBroadcast()
7297 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleReverse()
7319 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleSwap()
7341 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBitmaskPerm()
7403 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleMacro()
7467 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMacro()
7512 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMode()
7600 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtMubufImpl()
7605 int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); in cvtMubufImpl()
7734 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::tfe) != -1) in cvtMIMG()
7754 IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC; in cvtSMEMAtomic()
7759 int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode()); in cvtSMEMAtomic()
7796 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset)) in cvtSMEMAtomic()
8034 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3DstOpSelOnly()
8039 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3DstOpSelOnly()
8040 AMDGPU::OpName::src1, in cvtVOP3DstOpSelOnly()
8041 AMDGPU::OpName::src2 }; in cvtVOP3DstOpSelOnly()
8043 SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1; in cvtVOP3DstOpSelOnly()
8050 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in cvtVOP3DstOpSelOnly()
8070 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS in isRegOrImmWithInputMods()
8105 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) { in cvtVOP3Interp()
8109 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3Interp()
8113 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3Interp()
8142 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVINTERP()
8151 const int Ops[] = { AMDGPU::OpName::src0, in cvtVINTERP()
8152 AMDGPU::OpName::src1, in cvtVINTERP()
8153 AMDGPU::OpName::src2 }; in cvtVINTERP()
8154 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVINTERP()
8155 AMDGPU::OpName::src1_modifiers, in cvtVINTERP()
8156 AMDGPU::OpName::src2_modifiers }; in cvtVINTERP()
8161 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVINTERP()
8165 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVINTERP()
8170 if (ModOps[J] == AMDGPU::OpName::src0_modifiers && in cvtVINTERP()
8188 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) { in cvtVOP3()
8214 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3()
8218 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3()
8226 if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || in cvtVOP3()
8227 Opc == AMDGPU::V_MAC_F32_e64_gfx10 || in cvtVOP3()
8228 Opc == AMDGPU::V_MAC_F32_e64_vi || in cvtVOP3()
8229 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || in cvtVOP3()
8230 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
8231 Opc == AMDGPU::V_MAC_F16_e64_vi || in cvtVOP3()
8232 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a || in cvtVOP3()
8233 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 || in cvtVOP3()
8234 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 || in cvtVOP3()
8235 Opc == AMDGPU::V_FMAC_F32_e64_vi || in cvtVOP3()
8236 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
8237 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || in cvtVOP3()
8238 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 || in cvtVOP3()
8239 Opc == AMDGPU::V_FMAC_F16_e64_gfx11) { in cvtVOP3()
8241 std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers)); in cvtVOP3()
8261 if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi || in cvtVOP3P()
8262 Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) { in cvtVOP3P()
8267 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) { in cvtVOP3P()
8275 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3P()
8280 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in cvtVOP3P()
8287 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); in cvtVOP3P()
8293 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3P()
8294 AMDGPU::OpName::src1, in cvtVOP3P()
8295 AMDGPU::OpName::src2 }; in cvtVOP3P()
8296 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVOP3P()
8297 AMDGPU::OpName::src1_modifiers, in cvtVOP3P()
8298 AMDGPU::OpName::src2_modifiers }; in cvtVOP3P()
8312 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi); in cvtVOP3P()
8318 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVOP3P()
8322 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVOP3P()
8410 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vsrc1X) != -1; in cvtVOPD()
8412 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::immDeferred) != -1 || in cvtVOPD()
8413 (HasVsrc1X && (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::imm) == in cvtVOPD()
8415 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::imm) == in cvtVOPD()
8419 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vsrc1Y) != -1; in cvtVOPD()
8421 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::immDeferred) != -1 || in cvtVOPD()
8422 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::imm) >= in cvtVOPD()
8472 using namespace AMDGPU::DPP; in isDPPCtrl()
8544 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId); in parseDimId()
8671 using namespace AMDGPU::DPP; in parseDPPCtrlSel()
8719 using namespace AMDGPU::DPP; in parseDPPCtrl()
8776 bool HasModifiers = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1; in cvtVOP3DPP()
8812 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3DPP()
8815 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3DPP()
8822 else if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { in cvtVOP3DPP()
8828 using namespace llvm::AMDGPU::DPP; in cvtVOP3DPP()
8835 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) { in cvtVOP3DPP()
8846 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1; in cvtDPP()
8901 using namespace llvm::AMDGPU::DPP; in cvtDPP()
8907 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) { in cvtDPP()
8920 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
8954 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
9006 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()
9021 (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) { in cvtSDWA()
9049 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 && in cvtSDWA()
9050 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 && in cvtSDWA()
9051 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) { in cvtSDWA()
9055 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in cvtSDWA()
9056 AMDGPU::OpName::clamp) != -1) { in cvtSDWA()
9060 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in cvtSDWA()
9061 AMDGPU::OpName::omod) != -1) { in cvtSDWA()
9065 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in cvtSDWA()
9066 AMDGPU::OpName::dst_sel) != -1) { in cvtSDWA()
9070 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in cvtSDWA()
9071 AMDGPU::OpName::dst_unused) != -1) { in cvtSDWA()
9081 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
9091 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1) in cvtSDWA()
9104 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in cvtSDWA()
9105 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in cvtSDWA()
9108 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); in cvtSDWA()