Lines Matching refs:AMDGPU
315 return AMDGPU::getMUBUFElements(Opc); in getOpcodeWidth()
319 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
323 return AMDGPU::getMTBUFElements(Opc); in getOpcodeWidth()
327 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
328 case AMDGPU::GLOBAL_LOAD_DWORD: in getOpcodeWidth()
329 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getOpcodeWidth()
330 case AMDGPU::GLOBAL_STORE_DWORD: in getOpcodeWidth()
331 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getOpcodeWidth()
332 case AMDGPU::FLAT_LOAD_DWORD: in getOpcodeWidth()
333 case AMDGPU::FLAT_STORE_DWORD: in getOpcodeWidth()
335 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getOpcodeWidth()
336 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getOpcodeWidth()
337 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getOpcodeWidth()
338 case AMDGPU::GLOBAL_STORE_DWORDX2: in getOpcodeWidth()
339 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getOpcodeWidth()
340 case AMDGPU::FLAT_LOAD_DWORDX2: in getOpcodeWidth()
341 case AMDGPU::FLAT_STORE_DWORDX2: in getOpcodeWidth()
343 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getOpcodeWidth()
344 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getOpcodeWidth()
345 case AMDGPU::GLOBAL_STORE_DWORDX3: in getOpcodeWidth()
346 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getOpcodeWidth()
347 case AMDGPU::FLAT_LOAD_DWORDX3: in getOpcodeWidth()
348 case AMDGPU::FLAT_STORE_DWORDX3: in getOpcodeWidth()
350 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getOpcodeWidth()
351 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getOpcodeWidth()
352 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getOpcodeWidth()
353 case AMDGPU::GLOBAL_STORE_DWORDX4: in getOpcodeWidth()
354 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getOpcodeWidth()
355 case AMDGPU::FLAT_LOAD_DWORDX4: in getOpcodeWidth()
356 case AMDGPU::FLAT_STORE_DWORDX4: in getOpcodeWidth()
358 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getOpcodeWidth()
360 case AMDGPU::DS_READ_B32: LLVM_FALLTHROUGH; in getOpcodeWidth()
361 case AMDGPU::DS_READ_B32_gfx9: LLVM_FALLTHROUGH; in getOpcodeWidth()
362 case AMDGPU::DS_WRITE_B32: LLVM_FALLTHROUGH; in getOpcodeWidth()
363 case AMDGPU::DS_WRITE_B32_gfx9: in getOpcodeWidth()
365 case AMDGPU::DS_READ_B64: LLVM_FALLTHROUGH; in getOpcodeWidth()
366 case AMDGPU::DS_READ_B64_gfx9: LLVM_FALLTHROUGH; in getOpcodeWidth()
367 case AMDGPU::DS_WRITE_B64: LLVM_FALLTHROUGH; in getOpcodeWidth()
368 case AMDGPU::DS_WRITE_B64_gfx9: in getOpcodeWidth()
380 switch (AMDGPU::getMUBUFBaseOpcode(Opc)) { in getInstClass()
383 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getInstClass()
384 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: in getInstClass()
385 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getInstClass()
386 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: in getInstClass()
388 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getInstClass()
389 case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: in getInstClass()
390 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getInstClass()
391 case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: in getInstClass()
397 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1 && in getInstClass()
398 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) == -1) in getInstClass()
401 if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH) in getInstClass()
410 switch (AMDGPU::getMTBUFBaseOpcode(Opc)) { in getInstClass()
413 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN: in getInstClass()
414 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_exact: in getInstClass()
415 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET: in getInstClass()
416 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_exact: in getInstClass()
418 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN: in getInstClass()
419 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact: in getInstClass()
420 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET: in getInstClass()
421 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact: in getInstClass()
426 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstClass()
427 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstClass()
428 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstClass()
429 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstClass()
431 case AMDGPU::DS_READ_B32: in getInstClass()
432 case AMDGPU::DS_READ_B32_gfx9: in getInstClass()
433 case AMDGPU::DS_READ_B64: in getInstClass()
434 case AMDGPU::DS_READ_B64_gfx9: in getInstClass()
436 case AMDGPU::DS_WRITE_B32: in getInstClass()
437 case AMDGPU::DS_WRITE_B32_gfx9: in getInstClass()
438 case AMDGPU::DS_WRITE_B64: in getInstClass()
439 case AMDGPU::DS_WRITE_B64_gfx9: in getInstClass()
441 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstClass()
442 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstClass()
443 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstClass()
444 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstClass()
445 case AMDGPU::FLAT_LOAD_DWORD: in getInstClass()
446 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstClass()
447 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstClass()
448 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstClass()
450 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstClass()
451 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstClass()
452 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstClass()
453 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstClass()
455 case AMDGPU::GLOBAL_STORE_DWORD: in getInstClass()
456 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstClass()
457 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstClass()
458 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstClass()
459 case AMDGPU::FLAT_STORE_DWORD: in getInstClass()
460 case AMDGPU::FLAT_STORE_DWORDX2: in getInstClass()
461 case AMDGPU::FLAT_STORE_DWORDX3: in getInstClass()
462 case AMDGPU::FLAT_STORE_DWORDX4: in getInstClass()
464 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstClass()
465 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstClass()
466 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstClass()
467 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstClass()
479 return AMDGPU::getMUBUFBaseOpcode(Opc); in getInstSubclass()
481 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
486 return AMDGPU::getMTBUFBaseOpcode(Opc); in getInstSubclass()
488 case AMDGPU::DS_READ_B32: in getInstSubclass()
489 case AMDGPU::DS_READ_B32_gfx9: in getInstSubclass()
490 case AMDGPU::DS_READ_B64: in getInstSubclass()
491 case AMDGPU::DS_READ_B64_gfx9: in getInstSubclass()
492 case AMDGPU::DS_WRITE_B32: in getInstSubclass()
493 case AMDGPU::DS_WRITE_B32_gfx9: in getInstSubclass()
494 case AMDGPU::DS_WRITE_B64: in getInstSubclass()
495 case AMDGPU::DS_WRITE_B64_gfx9: in getInstSubclass()
497 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstSubclass()
498 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstSubclass()
499 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstSubclass()
500 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getInstSubclass()
501 return AMDGPU::S_BUFFER_LOAD_DWORD_IMM; in getInstSubclass()
502 case AMDGPU::GLOBAL_LOAD_DWORD: in getInstSubclass()
503 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getInstSubclass()
504 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getInstSubclass()
505 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getInstSubclass()
506 case AMDGPU::FLAT_LOAD_DWORD: in getInstSubclass()
507 case AMDGPU::FLAT_LOAD_DWORDX2: in getInstSubclass()
508 case AMDGPU::FLAT_LOAD_DWORDX3: in getInstSubclass()
509 case AMDGPU::FLAT_LOAD_DWORDX4: in getInstSubclass()
510 return AMDGPU::FLAT_LOAD_DWORD; in getInstSubclass()
511 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getInstSubclass()
512 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getInstSubclass()
513 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getInstSubclass()
514 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getInstSubclass()
515 return AMDGPU::GLOBAL_LOAD_DWORD_SADDR; in getInstSubclass()
516 case AMDGPU::GLOBAL_STORE_DWORD: in getInstSubclass()
517 case AMDGPU::GLOBAL_STORE_DWORDX2: in getInstSubclass()
518 case AMDGPU::GLOBAL_STORE_DWORDX3: in getInstSubclass()
519 case AMDGPU::GLOBAL_STORE_DWORDX4: in getInstSubclass()
520 case AMDGPU::FLAT_STORE_DWORD: in getInstSubclass()
521 case AMDGPU::FLAT_STORE_DWORDX2: in getInstSubclass()
522 case AMDGPU::FLAT_STORE_DWORDX3: in getInstSubclass()
523 case AMDGPU::FLAT_STORE_DWORDX4: in getInstSubclass()
524 return AMDGPU::FLAT_STORE_DWORD; in getInstSubclass()
525 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getInstSubclass()
526 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getInstSubclass()
527 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getInstSubclass()
528 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getInstSubclass()
529 return AMDGPU::GLOBAL_STORE_DWORD_SADDR; in getInstSubclass()
555 if (AMDGPU::getMUBUFHasVAddr(Opc)) in getRegs()
557 if (AMDGPU::getMUBUFHasSrsrc(Opc)) in getRegs()
559 if (AMDGPU::getMUBUFHasSoffset(Opc)) in getRegs()
566 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
568 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in getRegs()
574 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
575 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler) in getRegs()
581 if (AMDGPU::getMTBUFHasVAddr(Opc)) in getRegs()
583 if (AMDGPU::getMTBUFHasSrsrc(Opc)) in getRegs()
585 if (AMDGPU::getMTBUFHasSoffset(Opc)) in getRegs()
594 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getRegs()
595 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getRegs()
596 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getRegs()
597 case AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM: in getRegs()
600 case AMDGPU::DS_READ_B32: in getRegs()
601 case AMDGPU::DS_READ_B64: in getRegs()
602 case AMDGPU::DS_READ_B32_gfx9: in getRegs()
603 case AMDGPU::DS_READ_B64_gfx9: in getRegs()
604 case AMDGPU::DS_WRITE_B32: in getRegs()
605 case AMDGPU::DS_WRITE_B64: in getRegs()
606 case AMDGPU::DS_WRITE_B32_gfx9: in getRegs()
607 case AMDGPU::DS_WRITE_B64_gfx9: in getRegs()
610 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getRegs()
611 case AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR: in getRegs()
612 case AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR: in getRegs()
613 case AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR: in getRegs()
614 case AMDGPU::GLOBAL_STORE_DWORD_SADDR: in getRegs()
615 case AMDGPU::GLOBAL_STORE_DWORDX2_SADDR: in getRegs()
616 case AMDGPU::GLOBAL_STORE_DWORDX3_SADDR: in getRegs()
617 case AMDGPU::GLOBAL_STORE_DWORDX4_SADDR: in getRegs()
620 case AMDGPU::GLOBAL_LOAD_DWORD: in getRegs()
621 case AMDGPU::GLOBAL_LOAD_DWORDX2: in getRegs()
622 case AMDGPU::GLOBAL_LOAD_DWORDX3: in getRegs()
623 case AMDGPU::GLOBAL_LOAD_DWORDX4: in getRegs()
624 case AMDGPU::GLOBAL_STORE_DWORD: in getRegs()
625 case AMDGPU::GLOBAL_STORE_DWORDX2: in getRegs()
626 case AMDGPU::GLOBAL_STORE_DWORDX3: in getRegs()
627 case AMDGPU::GLOBAL_STORE_DWORDX4: in getRegs()
628 case AMDGPU::FLAT_LOAD_DWORD: in getRegs()
629 case AMDGPU::FLAT_LOAD_DWORDX2: in getRegs()
630 case AMDGPU::FLAT_LOAD_DWORDX3: in getRegs()
631 case AMDGPU::FLAT_LOAD_DWORDX4: in getRegs()
632 case AMDGPU::FLAT_STORE_DWORD: in getRegs()
633 case AMDGPU::FLAT_STORE_DWORDX2: in getRegs()
634 case AMDGPU::FLAT_STORE_DWORDX3: in getRegs()
635 case AMDGPU::FLAT_STORE_DWORDX4: in getRegs()
655 (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8 in setMI()
660 (Opc == AMDGPU::DS_WRITE_B64 || Opc == AMDGPU::DS_WRITE_B64_gfx9) ? 8 in setMI()
664 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4); in setMI()
672 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
676 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
681 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
688 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
696 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
699 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
702 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
705 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in setMI()
708 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset); in setMI()
711 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
714 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in setMI()
717 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::ssamp); in setMI()
800 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
801 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
807 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16, in dmasksCanBeCombined()
808 AMDGPU::OpName::unorm, AMDGPU::OpName::da, in dmasksCanBeCombined()
809 AMDGPU::OpName::r128, AMDGPU::OpName::a16}; in dmasksCanBeCombined()
812 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); in dmasksCanBeCombined()
813 if (AMDGPU::getNamedOperandIdx(Paired.I->getOpcode(), op) != Idx) in dmasksCanBeCombined()
837 const llvm::AMDGPU::GcnBufferFormatInfo *OldFormatInfo = in getBufferFormatWithCompCount()
838 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormat, STI); in getBufferFormatWithCompCount()
842 const llvm::AMDGPU::GcnBufferFormatInfo *NewFormatInfo = in getBufferFormatWithCompCount()
843 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormatInfo->BitsPerComp, in getBufferFormatWithCompCount()
883 const llvm::AMDGPU::GcnBufferFormatInfo *Info0 = in offsetsCanBeCombined()
884 llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI); in offsetsCanBeCombined()
887 const llvm::AMDGPU::GcnBufferFormatInfo *Info1 = in offsetsCanBeCombined()
888 llvm::AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI); in offsetsCanBeCombined()
997 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
1000 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
1003 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
1006 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
1009 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
1072 return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in read2Opcode()
1073 return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9; in read2Opcode()
1078 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in read2ST64Opcode()
1080 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9 in read2ST64Opcode()
1081 : AMDGPU::DS_READ2ST64_B64_gfx9; in read2ST64Opcode()
1091 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1093 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1094 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1101 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
1102 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
1124 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair()
1125 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1128 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair()
1167 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in write2Opcode()
1168 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9 in write2Opcode()
1169 : AMDGPU::DS_WRITE2_B64_gfx9; in write2Opcode()
1174 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 in write2ST64Opcode()
1175 : AMDGPU::DS_WRITE2ST64_B64; in write2ST64Opcode()
1177 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9 in write2ST64Opcode()
1178 : AMDGPU::DS_WRITE2ST64_B64_gfx9; in write2ST64Opcode()
1189 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1191 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1193 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1216 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair()
1217 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1220 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair()
1259 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
1281 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1282 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeImagePair()
1315 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
1326 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1327 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1360 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1368 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1369 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1382 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1383 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1416 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1427 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1428 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1442 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1443 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1473 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1474 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1476 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeTBufferStorePair()
1488 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1499 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1500 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1526 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatLoadPair()
1530 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatLoadPair()
1541 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1542 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeFlatLoadPair()
1572 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1573 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeFlatStorePair()
1575 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeFlatStorePair()
1582 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)) in mergeFlatStorePair()
1585 if (auto *SAddr = TII->getNamedOperand(*CI.I, AMDGPU::OpName::saddr)) in mergeFlatStorePair()
1606 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1610 return AMDGPU::getMTBUFOpcode(AMDGPU::getMTBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1620 return AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM; in getNewOpcode()
1622 return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM; in getNewOpcode()
1624 return AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM; in getNewOpcode()
1631 return AMDGPU::GLOBAL_LOAD_DWORDX2; in getNewOpcode()
1633 return AMDGPU::GLOBAL_LOAD_DWORDX3; in getNewOpcode()
1635 return AMDGPU::GLOBAL_LOAD_DWORDX4; in getNewOpcode()
1642 return AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR; in getNewOpcode()
1644 return AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR; in getNewOpcode()
1646 return AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR; in getNewOpcode()
1653 return AMDGPU::GLOBAL_STORE_DWORDX2; in getNewOpcode()
1655 return AMDGPU::GLOBAL_STORE_DWORDX3; in getNewOpcode()
1657 return AMDGPU::GLOBAL_STORE_DWORDX4; in getNewOpcode()
1664 return AMDGPU::GLOBAL_STORE_DWORDX2_SADDR; in getNewOpcode()
1666 return AMDGPU::GLOBAL_STORE_DWORDX3_SADDR; in getNewOpcode()
1668 return AMDGPU::GLOBAL_STORE_DWORDX4_SADDR; in getNewOpcode()
1675 return AMDGPU::FLAT_LOAD_DWORDX2; in getNewOpcode()
1677 return AMDGPU::FLAT_LOAD_DWORDX3; in getNewOpcode()
1679 return AMDGPU::FLAT_LOAD_DWORDX4; in getNewOpcode()
1686 return AMDGPU::FLAT_STORE_DWORDX2; in getNewOpcode()
1688 return AMDGPU::FLAT_STORE_DWORDX3; in getNewOpcode()
1690 return AMDGPU::FLAT_STORE_DWORDX4; in getNewOpcode()
1695 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); in getNewOpcode()
1710 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1711 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs()
1712 {AMDGPU::sub2, AMDGPU::sub2_sub3, AMDGPU::sub2_sub3_sub4, AMDGPU::sub2_sub3_sub4_sub5}, in getSubRegIdxs()
1713 {AMDGPU::sub3, AMDGPU::sub3_sub4, AMDGPU::sub3_sub4_sub5, AMDGPU::sub3_sub4_sub5_sub6}, in getSubRegIdxs()
1714 {AMDGPU::sub4, AMDGPU::sub4_sub5, AMDGPU::sub4_sub5_sub6, AMDGPU::sub4_sub5_sub6_sub7}, in getSubRegIdxs()
1739 return &AMDGPU::SReg_64_XEXECRegClass; in getTargetRegisterClass()
1741 return &AMDGPU::SGPR_128RegClass; in getTargetRegisterClass()
1743 return &AMDGPU::SGPR_256RegClass; in getTargetRegisterClass()
1745 return &AMDGPU::SGPR_512RegClass; in getTargetRegisterClass()
1771 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1772 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1774 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1786 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1795 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1796 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1814 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in createRegOrImm()
1817 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1844 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in computeBase()
1848 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1849 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1851 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1860 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1873 .addImm(AMDGPU::sub0) in computeBase()
1875 .addImm(AMDGPU::sub1); in computeBase()
1886 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
1889 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
1901 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 || in extractConstOffset()
1924 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE in processBaseWithConstOffset()
1936 if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 || in processBaseWithConstOffset()
1937 !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64) in processBaseWithConstOffset()
1940 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1941 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1952 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1953 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1980 if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0) in promoteConstantOffsetToImm()
1984 TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != nullptr) in promoteConstantOffsetToImm()
1992 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
1998 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2057 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
2061 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
2170 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); in collectMergeableInsts()