Lines Matching refs:AMDGPU
90 Register TmpVGPR = AMDGPU::NoRegister;
96 Register SavedExecReg = AMDGPU::NoRegister;
130 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
131 MovOpc = AMDGPU::S_MOV_B32; in SGPRSpillBuilder()
132 NotOpc = AMDGPU::S_NOT_B32; in SGPRSpillBuilder()
134 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
135 MovOpc = AMDGPU::S_MOV_B64; in SGPRSpillBuilder()
136 NotOpc = AMDGPU::S_NOT_B64; in SGPRSpillBuilder()
139 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
141 SuperReg != AMDGPU::EXEC && "exec should never spill"); in SGPRSpillBuilder()
173 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false); in prepare()
183 TmpVGPR = AMDGPU::VGPR0; in prepare()
200 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
220 if (RS->isRegUsed(AMDGPU::SCC)) in prepare()
295 if (RS->isRegUsed(AMDGPU::SCC)) in readWriteTmpVGPR()
320 : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST), in SIRegisterInfo()
323 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
324 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) && in SIRegisterInfo()
325 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
326 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() == in SIRegisterInfo()
327 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
332 *MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this)); in SIRegisterInfo()
333 for (auto Reg : AMDGPU::VGPR_HI16RegClass) in SIRegisterInfo()
361 Row.fill(AMDGPU::NoSubRegister); in SIRegisterInfo()
404 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
443 if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass) in getLargestLegalSuperClass()
444 return &AMDGPU::AV_32RegClass; in getLargestLegalSuperClass()
445 if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass) in getLargestLegalSuperClass()
446 return &AMDGPU::AV_64RegClass; in getLargestLegalSuperClass()
447 if (RC == &AMDGPU::VReg_64_Align2RegClass || in getLargestLegalSuperClass()
448 RC == &AMDGPU::AReg_64_Align2RegClass) in getLargestLegalSuperClass()
449 return &AMDGPU::AV_64_Align2RegClass; in getLargestLegalSuperClass()
450 if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass) in getLargestLegalSuperClass()
451 return &AMDGPU::AV_96RegClass; in getLargestLegalSuperClass()
452 if (RC == &AMDGPU::VReg_96_Align2RegClass || in getLargestLegalSuperClass()
453 RC == &AMDGPU::AReg_96_Align2RegClass) in getLargestLegalSuperClass()
454 return &AMDGPU::AV_96_Align2RegClass; in getLargestLegalSuperClass()
455 if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass) in getLargestLegalSuperClass()
456 return &AMDGPU::AV_128RegClass; in getLargestLegalSuperClass()
457 if (RC == &AMDGPU::VReg_128_Align2RegClass || in getLargestLegalSuperClass()
458 RC == &AMDGPU::AReg_128_Align2RegClass) in getLargestLegalSuperClass()
459 return &AMDGPU::AV_128_Align2RegClass; in getLargestLegalSuperClass()
460 if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass) in getLargestLegalSuperClass()
461 return &AMDGPU::AV_160RegClass; in getLargestLegalSuperClass()
462 if (RC == &AMDGPU::VReg_160_Align2RegClass || in getLargestLegalSuperClass()
463 RC == &AMDGPU::AReg_160_Align2RegClass) in getLargestLegalSuperClass()
464 return &AMDGPU::AV_160_Align2RegClass; in getLargestLegalSuperClass()
465 if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass) in getLargestLegalSuperClass()
466 return &AMDGPU::AV_192RegClass; in getLargestLegalSuperClass()
467 if (RC == &AMDGPU::VReg_192_Align2RegClass || in getLargestLegalSuperClass()
468 RC == &AMDGPU::AReg_192_Align2RegClass) in getLargestLegalSuperClass()
469 return &AMDGPU::AV_192_Align2RegClass; in getLargestLegalSuperClass()
470 if (RC == &AMDGPU::VReg_256RegClass || RC == &AMDGPU::AReg_256RegClass) in getLargestLegalSuperClass()
471 return &AMDGPU::AV_256RegClass; in getLargestLegalSuperClass()
472 if (RC == &AMDGPU::VReg_256_Align2RegClass || in getLargestLegalSuperClass()
473 RC == &AMDGPU::AReg_256_Align2RegClass) in getLargestLegalSuperClass()
474 return &AMDGPU::AV_256_Align2RegClass; in getLargestLegalSuperClass()
475 if (RC == &AMDGPU::VReg_512RegClass || RC == &AMDGPU::AReg_512RegClass) in getLargestLegalSuperClass()
476 return &AMDGPU::AV_512RegClass; in getLargestLegalSuperClass()
477 if (RC == &AMDGPU::VReg_512_Align2RegClass || in getLargestLegalSuperClass()
478 RC == &AMDGPU::AReg_512_Align2RegClass) in getLargestLegalSuperClass()
479 return &AMDGPU::AV_512_Align2RegClass; in getLargestLegalSuperClass()
480 if (RC == &AMDGPU::VReg_1024RegClass || RC == &AMDGPU::AReg_1024RegClass) in getLargestLegalSuperClass()
481 return &AMDGPU::AV_1024RegClass; in getLargestLegalSuperClass()
482 if (RC == &AMDGPU::VReg_1024_Align2RegClass || in getLargestLegalSuperClass()
483 RC == &AMDGPU::AReg_1024_Align2RegClass) in getLargestLegalSuperClass()
484 return &AMDGPU::AV_1024_Align2RegClass; in getLargestLegalSuperClass()
511 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; } in getBaseRegister()
541 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg()
542 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
547 Reserved.set(AMDGPU::MODE); in getReservedRegs()
555 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
556 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
559 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
562 reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ); in getReservedRegs()
563 reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ); in getReservedRegs()
564 reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC); in getReservedRegs()
567 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
568 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
569 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
570 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); in getReservedRegs()
573 reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID); in getReservedRegs()
576 reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK); in getReservedRegs()
579 reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT); in getReservedRegs()
582 reserveRegisterTuples(Reserved, AMDGPU::TBA); in getReservedRegs()
583 reserveRegisterTuples(Reserved, AMDGPU::TMA); in getReservedRegs()
584 reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1); in getReservedRegs()
585 reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3); in getReservedRegs()
586 reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5); in getReservedRegs()
587 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7); in getReservedRegs()
588 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9); in getReservedRegs()
589 reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11); in getReservedRegs()
590 reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13); in getReservedRegs()
591 reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15); in getReservedRegs()
594 reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL64); in getReservedRegs()
599 Reserved.set(AMDGPU::VCC); in getReservedRegs()
600 Reserved.set(AMDGPU::VCC_HI); in getReservedRegs()
606 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs(); in getReservedRegs()
608 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i); in getReservedRegs()
612 for (auto Reg : AMDGPU::SReg_32RegClass) { in getReservedRegs()
613 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
614 Register Low = getSubReg(Reg, AMDGPU::lo16); in getReservedRegs()
616 if (!AMDGPU::SGPR_LO16RegClass.contains(Low)) in getReservedRegs()
621 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
653 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs(); in getReservedRegs()
658 unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
663 for (auto Reg : AMDGPU::AGPR_32RegClass) { in getReservedRegs()
664 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
689 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i); in getReservedRegs()
694 unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
773 int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getScratchInstrOffset()
774 AMDGPU::OpName::offset); in getScratchInstrOffset()
783 assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
784 AMDGPU::OpName::vaddr) || in getFrameIndexInstrOffset()
785 (Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
786 AMDGPU::OpName::saddr))) && in getFrameIndexInstrOffset()
818 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 in materializeFrameBaseRegister()
819 : AMDGPU::V_MOV_B32_e32; in materializeFrameBaseRegister()
822 ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass in materializeFrameBaseRegister()
823 : &AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
831 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister()
834 ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass in materializeFrameBaseRegister()
835 : &AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
837 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
843 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg) in materializeFrameBaseRegister()
876 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
877 : AMDGPU::OpName::vaddr); in resolveFrameIndex()
879 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
895 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
927 return &AMDGPU::VGPR_32RegClass; in getPointerRegClass()
941 case AMDGPU::SI_SPILL_S1024_SAVE: in getNumSubRegsForSpillOp()
942 case AMDGPU::SI_SPILL_S1024_RESTORE: in getNumSubRegsForSpillOp()
943 case AMDGPU::SI_SPILL_V1024_SAVE: in getNumSubRegsForSpillOp()
944 case AMDGPU::SI_SPILL_V1024_RESTORE: in getNumSubRegsForSpillOp()
945 case AMDGPU::SI_SPILL_A1024_SAVE: in getNumSubRegsForSpillOp()
946 case AMDGPU::SI_SPILL_A1024_RESTORE: in getNumSubRegsForSpillOp()
947 case AMDGPU::SI_SPILL_AV1024_SAVE: in getNumSubRegsForSpillOp()
948 case AMDGPU::SI_SPILL_AV1024_RESTORE: in getNumSubRegsForSpillOp()
950 case AMDGPU::SI_SPILL_S512_SAVE: in getNumSubRegsForSpillOp()
951 case AMDGPU::SI_SPILL_S512_RESTORE: in getNumSubRegsForSpillOp()
952 case AMDGPU::SI_SPILL_V512_SAVE: in getNumSubRegsForSpillOp()
953 case AMDGPU::SI_SPILL_V512_RESTORE: in getNumSubRegsForSpillOp()
954 case AMDGPU::SI_SPILL_A512_SAVE: in getNumSubRegsForSpillOp()
955 case AMDGPU::SI_SPILL_A512_RESTORE: in getNumSubRegsForSpillOp()
956 case AMDGPU::SI_SPILL_AV512_SAVE: in getNumSubRegsForSpillOp()
957 case AMDGPU::SI_SPILL_AV512_RESTORE: in getNumSubRegsForSpillOp()
959 case AMDGPU::SI_SPILL_S256_SAVE: in getNumSubRegsForSpillOp()
960 case AMDGPU::SI_SPILL_S256_RESTORE: in getNumSubRegsForSpillOp()
961 case AMDGPU::SI_SPILL_V256_SAVE: in getNumSubRegsForSpillOp()
962 case AMDGPU::SI_SPILL_V256_RESTORE: in getNumSubRegsForSpillOp()
963 case AMDGPU::SI_SPILL_A256_SAVE: in getNumSubRegsForSpillOp()
964 case AMDGPU::SI_SPILL_A256_RESTORE: in getNumSubRegsForSpillOp()
965 case AMDGPU::SI_SPILL_AV256_SAVE: in getNumSubRegsForSpillOp()
966 case AMDGPU::SI_SPILL_AV256_RESTORE: in getNumSubRegsForSpillOp()
968 case AMDGPU::SI_SPILL_S224_SAVE: in getNumSubRegsForSpillOp()
969 case AMDGPU::SI_SPILL_S224_RESTORE: in getNumSubRegsForSpillOp()
970 case AMDGPU::SI_SPILL_V224_SAVE: in getNumSubRegsForSpillOp()
971 case AMDGPU::SI_SPILL_V224_RESTORE: in getNumSubRegsForSpillOp()
972 case AMDGPU::SI_SPILL_A224_SAVE: in getNumSubRegsForSpillOp()
973 case AMDGPU::SI_SPILL_A224_RESTORE: in getNumSubRegsForSpillOp()
974 case AMDGPU::SI_SPILL_AV224_SAVE: in getNumSubRegsForSpillOp()
975 case AMDGPU::SI_SPILL_AV224_RESTORE: in getNumSubRegsForSpillOp()
977 case AMDGPU::SI_SPILL_S192_SAVE: in getNumSubRegsForSpillOp()
978 case AMDGPU::SI_SPILL_S192_RESTORE: in getNumSubRegsForSpillOp()
979 case AMDGPU::SI_SPILL_V192_SAVE: in getNumSubRegsForSpillOp()
980 case AMDGPU::SI_SPILL_V192_RESTORE: in getNumSubRegsForSpillOp()
981 case AMDGPU::SI_SPILL_A192_SAVE: in getNumSubRegsForSpillOp()
982 case AMDGPU::SI_SPILL_A192_RESTORE: in getNumSubRegsForSpillOp()
983 case AMDGPU::SI_SPILL_AV192_SAVE: in getNumSubRegsForSpillOp()
984 case AMDGPU::SI_SPILL_AV192_RESTORE: in getNumSubRegsForSpillOp()
986 case AMDGPU::SI_SPILL_S160_SAVE: in getNumSubRegsForSpillOp()
987 case AMDGPU::SI_SPILL_S160_RESTORE: in getNumSubRegsForSpillOp()
988 case AMDGPU::SI_SPILL_V160_SAVE: in getNumSubRegsForSpillOp()
989 case AMDGPU::SI_SPILL_V160_RESTORE: in getNumSubRegsForSpillOp()
990 case AMDGPU::SI_SPILL_A160_SAVE: in getNumSubRegsForSpillOp()
991 case AMDGPU::SI_SPILL_A160_RESTORE: in getNumSubRegsForSpillOp()
992 case AMDGPU::SI_SPILL_AV160_SAVE: in getNumSubRegsForSpillOp()
993 case AMDGPU::SI_SPILL_AV160_RESTORE: in getNumSubRegsForSpillOp()
995 case AMDGPU::SI_SPILL_S128_SAVE: in getNumSubRegsForSpillOp()
996 case AMDGPU::SI_SPILL_S128_RESTORE: in getNumSubRegsForSpillOp()
997 case AMDGPU::SI_SPILL_V128_SAVE: in getNumSubRegsForSpillOp()
998 case AMDGPU::SI_SPILL_V128_RESTORE: in getNumSubRegsForSpillOp()
999 case AMDGPU::SI_SPILL_A128_SAVE: in getNumSubRegsForSpillOp()
1000 case AMDGPU::SI_SPILL_A128_RESTORE: in getNumSubRegsForSpillOp()
1001 case AMDGPU::SI_SPILL_AV128_SAVE: in getNumSubRegsForSpillOp()
1002 case AMDGPU::SI_SPILL_AV128_RESTORE: in getNumSubRegsForSpillOp()
1004 case AMDGPU::SI_SPILL_S96_SAVE: in getNumSubRegsForSpillOp()
1005 case AMDGPU::SI_SPILL_S96_RESTORE: in getNumSubRegsForSpillOp()
1006 case AMDGPU::SI_SPILL_V96_SAVE: in getNumSubRegsForSpillOp()
1007 case AMDGPU::SI_SPILL_V96_RESTORE: in getNumSubRegsForSpillOp()
1008 case AMDGPU::SI_SPILL_A96_SAVE: in getNumSubRegsForSpillOp()
1009 case AMDGPU::SI_SPILL_A96_RESTORE: in getNumSubRegsForSpillOp()
1010 case AMDGPU::SI_SPILL_AV96_SAVE: in getNumSubRegsForSpillOp()
1011 case AMDGPU::SI_SPILL_AV96_RESTORE: in getNumSubRegsForSpillOp()
1013 case AMDGPU::SI_SPILL_S64_SAVE: in getNumSubRegsForSpillOp()
1014 case AMDGPU::SI_SPILL_S64_RESTORE: in getNumSubRegsForSpillOp()
1015 case AMDGPU::SI_SPILL_V64_SAVE: in getNumSubRegsForSpillOp()
1016 case AMDGPU::SI_SPILL_V64_RESTORE: in getNumSubRegsForSpillOp()
1017 case AMDGPU::SI_SPILL_A64_SAVE: in getNumSubRegsForSpillOp()
1018 case AMDGPU::SI_SPILL_A64_RESTORE: in getNumSubRegsForSpillOp()
1019 case AMDGPU::SI_SPILL_AV64_SAVE: in getNumSubRegsForSpillOp()
1020 case AMDGPU::SI_SPILL_AV64_RESTORE: in getNumSubRegsForSpillOp()
1022 case AMDGPU::SI_SPILL_S32_SAVE: in getNumSubRegsForSpillOp()
1023 case AMDGPU::SI_SPILL_S32_RESTORE: in getNumSubRegsForSpillOp()
1024 case AMDGPU::SI_SPILL_V32_SAVE: in getNumSubRegsForSpillOp()
1025 case AMDGPU::SI_SPILL_V32_RESTORE: in getNumSubRegsForSpillOp()
1026 case AMDGPU::SI_SPILL_A32_SAVE: in getNumSubRegsForSpillOp()
1027 case AMDGPU::SI_SPILL_A32_RESTORE: in getNumSubRegsForSpillOp()
1028 case AMDGPU::SI_SPILL_AV32_SAVE: in getNumSubRegsForSpillOp()
1029 case AMDGPU::SI_SPILL_AV32_RESTORE: in getNumSubRegsForSpillOp()
1037 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getOffsetMUBUFStore()
1038 return AMDGPU::BUFFER_STORE_DWORD_OFFSET; in getOffsetMUBUFStore()
1039 case AMDGPU::BUFFER_STORE_BYTE_OFFEN: in getOffsetMUBUFStore()
1040 return AMDGPU::BUFFER_STORE_BYTE_OFFSET; in getOffsetMUBUFStore()
1041 case AMDGPU::BUFFER_STORE_SHORT_OFFEN: in getOffsetMUBUFStore()
1042 return AMDGPU::BUFFER_STORE_SHORT_OFFSET; in getOffsetMUBUFStore()
1043 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN: in getOffsetMUBUFStore()
1044 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET; in getOffsetMUBUFStore()
1045 case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN: in getOffsetMUBUFStore()
1046 return AMDGPU::BUFFER_STORE_DWORDX3_OFFSET; in getOffsetMUBUFStore()
1047 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN: in getOffsetMUBUFStore()
1048 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET; in getOffsetMUBUFStore()
1049 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN: in getOffsetMUBUFStore()
1050 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET; in getOffsetMUBUFStore()
1051 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN: in getOffsetMUBUFStore()
1052 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET; in getOffsetMUBUFStore()
1060 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getOffsetMUBUFLoad()
1061 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in getOffsetMUBUFLoad()
1062 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN: in getOffsetMUBUFLoad()
1063 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET; in getOffsetMUBUFLoad()
1064 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN: in getOffsetMUBUFLoad()
1065 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET; in getOffsetMUBUFLoad()
1066 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN: in getOffsetMUBUFLoad()
1067 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET; in getOffsetMUBUFLoad()
1068 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN: in getOffsetMUBUFLoad()
1069 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET; in getOffsetMUBUFLoad()
1070 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN: in getOffsetMUBUFLoad()
1071 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET; in getOffsetMUBUFLoad()
1072 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN: in getOffsetMUBUFLoad()
1073 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET; in getOffsetMUBUFLoad()
1074 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN: in getOffsetMUBUFLoad()
1075 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET; in getOffsetMUBUFLoad()
1076 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
1077 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
1078 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
1079 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
1080 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
1081 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
1082 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
1083 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
1084 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN: in getOffsetMUBUFLoad()
1085 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET; in getOffsetMUBUFLoad()
1086 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN: in getOffsetMUBUFLoad()
1087 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET; in getOffsetMUBUFLoad()
1095 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getOffenMUBUFStore()
1096 return AMDGPU::BUFFER_STORE_DWORD_OFFEN; in getOffenMUBUFStore()
1097 case AMDGPU::BUFFER_STORE_BYTE_OFFSET: in getOffenMUBUFStore()
1098 return AMDGPU::BUFFER_STORE_BYTE_OFFEN; in getOffenMUBUFStore()
1099 case AMDGPU::BUFFER_STORE_SHORT_OFFSET: in getOffenMUBUFStore()
1100 return AMDGPU::BUFFER_STORE_SHORT_OFFEN; in getOffenMUBUFStore()
1101 case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET: in getOffenMUBUFStore()
1102 return AMDGPU::BUFFER_STORE_DWORDX2_OFFEN; in getOffenMUBUFStore()
1103 case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET: in getOffenMUBUFStore()
1104 return AMDGPU::BUFFER_STORE_DWORDX3_OFFEN; in getOffenMUBUFStore()
1105 case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET: in getOffenMUBUFStore()
1106 return AMDGPU::BUFFER_STORE_DWORDX4_OFFEN; in getOffenMUBUFStore()
1107 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET: in getOffenMUBUFStore()
1108 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN; in getOffenMUBUFStore()
1109 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET: in getOffenMUBUFStore()
1110 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN; in getOffenMUBUFStore()
1118 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getOffenMUBUFLoad()
1119 return AMDGPU::BUFFER_LOAD_DWORD_OFFEN; in getOffenMUBUFLoad()
1120 case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET: in getOffenMUBUFLoad()
1121 return AMDGPU::BUFFER_LOAD_UBYTE_OFFEN; in getOffenMUBUFLoad()
1122 case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET: in getOffenMUBUFLoad()
1123 return AMDGPU::BUFFER_LOAD_SBYTE_OFFEN; in getOffenMUBUFLoad()
1124 case AMDGPU::BUFFER_LOAD_USHORT_OFFSET: in getOffenMUBUFLoad()
1125 return AMDGPU::BUFFER_LOAD_USHORT_OFFEN; in getOffenMUBUFLoad()
1126 case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET: in getOffenMUBUFLoad()
1127 return AMDGPU::BUFFER_LOAD_SSHORT_OFFEN; in getOffenMUBUFLoad()
1128 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET: in getOffenMUBUFLoad()
1129 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN; in getOffenMUBUFLoad()
1130 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET: in getOffenMUBUFLoad()
1131 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN; in getOffenMUBUFLoad()
1132 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET: in getOffenMUBUFLoad()
1133 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN; in getOffenMUBUFLoad()
1134 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET: in getOffenMUBUFLoad()
1135 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN; in getOffenMUBUFLoad()
1136 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET: in getOffenMUBUFLoad()
1137 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN; in getOffenMUBUFLoad()
1138 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET: in getOffenMUBUFLoad()
1139 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN; in getOffenMUBUFLoad()
1140 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET: in getOffenMUBUFLoad()
1141 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN; in getOffenMUBUFLoad()
1142 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET: in getOffenMUBUFLoad()
1143 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN; in getOffenMUBUFLoad()
1144 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET: in getOffenMUBUFLoad()
1145 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN; in getOffenMUBUFLoad()
1162 if (Reg == AMDGPU::NoRegister) in spillVGPRtoAGPR()
1178 auto CopyMIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::COPY), Dst) in spillVGPRtoAGPR()
1183 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
1184 : AMDGPU::V_ACCVGPR_READ_B32_e64; in spillVGPRtoAGPR()
1210 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
1217 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
1218 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
1226 AMDGPU::OpName::vdata_in); in buildMUBUFOffsetLoadStore()
1236 bool HasVAddr = AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) != -1; in getFlatScratchSpillOpcode()
1239 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0; in getFlatScratchSpillOpcode()
1243 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1244 : AMDGPU::SCRATCH_LOAD_DWORD_SADDR; in getFlatScratchSpillOpcode()
1247 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR in getFlatScratchSpillOpcode()
1248 : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR; in getFlatScratchSpillOpcode()
1251 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR in getFlatScratchSpillOpcode()
1252 : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR; in getFlatScratchSpillOpcode()
1255 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR in getFlatScratchSpillOpcode()
1256 : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR; in getFlatScratchSpillOpcode()
1263 LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp); in getFlatScratchSpillOpcode()
1265 LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp); in getFlatScratchSpillOpcode()
1293 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore()
1336 if (ST.getConstantBusLimit(AMDGPU::V_ADD_U32_e64) >= 2) { in buildSpillLoadStore()
1337 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e64), TmpVGPR) in buildSpillLoadStore()
1342 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in buildSpillLoadStore()
1344 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32), TmpVGPR) in buildSpillLoadStore()
1350 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in buildSpillLoadStore()
1367 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
1370 CanClobberSCC = !RS->isRegUsed(AMDGPU::SCC); in buildSpillLoadStore()
1372 CanClobberSCC = !LiveRegs->contains(AMDGPU::SCC); in buildSpillLoadStore()
1373 for (MCRegister Reg : AMDGPU::SGPR_32RegClass) { in buildSpillLoadStore()
1381 if (ScratchOffsetReg != AMDGPU::NoRegister && !CanClobberSCC) in buildSpillLoadStore()
1388 TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore()
1391 for (MCRegister Reg : AMDGPU::VGPR_32RegClass) { in buildSpillLoadStore()
1431 } else if (ScratchOffsetReg == AMDGPU::NoRegister) { in buildSpillLoadStore()
1432 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset).addImm(Offset); in buildSpillLoadStore()
1435 auto Add = BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset) in buildSpillLoadStore()
1444 if (IsFlat && SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1445 assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 in buildSpillLoadStore()
1449 LoadStoreOp = AMDGPU::getFlatScratchInstSVfromSS(LoadStoreOp); in buildSpillLoadStore()
1452 LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp); in buildSpillLoadStore()
1560 TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), in buildSpillLoadStore()
1571 TmpOffsetVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore()
1594 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1617 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
1618 MIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), in buildSpillLoadStore()
1630 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset) in buildSpillLoadStore()
1655 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildVGPRSpillLoadStore()
1656 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in buildVGPRSpillLoadStore()
1660 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildVGPRSpillLoadStore()
1661 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in buildVGPRSpillLoadStore()
1701 SB.TII.get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) in spillSGPR()
1747 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillSGPR()
1808 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in restoreSGPR()
1843 SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1889 BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillEmergencySGPR()
1923 auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), in spillEmergencySGPR()
1946 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1947 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1948 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1949 case AMDGPU::SI_SPILL_S224_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1950 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1951 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1952 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1953 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1954 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1955 case AMDGPU::SI_SPILL_S32_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1957 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1958 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1959 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1960 case AMDGPU::SI_SPILL_S224_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1961 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1962 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1963 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1964 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1965 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1966 case AMDGPU::SI_SPILL_S32_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1994 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateFrameIndex()
1995 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateFrameIndex()
1996 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateFrameIndex()
1997 case AMDGPU::SI_SPILL_S224_SAVE: in eliminateFrameIndex()
1998 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateFrameIndex()
1999 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateFrameIndex()
2000 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateFrameIndex()
2001 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateFrameIndex()
2002 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateFrameIndex()
2003 case AMDGPU::SI_SPILL_S32_SAVE: { in eliminateFrameIndex()
2009 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateFrameIndex()
2010 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateFrameIndex()
2011 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateFrameIndex()
2012 case AMDGPU::SI_SPILL_S224_RESTORE: in eliminateFrameIndex()
2013 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateFrameIndex()
2014 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateFrameIndex()
2015 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateFrameIndex()
2016 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateFrameIndex()
2017 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateFrameIndex()
2018 case AMDGPU::SI_SPILL_S32_RESTORE: { in eliminateFrameIndex()
2024 case AMDGPU::SI_SPILL_V1024_SAVE: in eliminateFrameIndex()
2025 case AMDGPU::SI_SPILL_V512_SAVE: in eliminateFrameIndex()
2026 case AMDGPU::SI_SPILL_V256_SAVE: in eliminateFrameIndex()
2027 case AMDGPU::SI_SPILL_V224_SAVE: in eliminateFrameIndex()
2028 case AMDGPU::SI_SPILL_V192_SAVE: in eliminateFrameIndex()
2029 case AMDGPU::SI_SPILL_V160_SAVE: in eliminateFrameIndex()
2030 case AMDGPU::SI_SPILL_V128_SAVE: in eliminateFrameIndex()
2031 case AMDGPU::SI_SPILL_V96_SAVE: in eliminateFrameIndex()
2032 case AMDGPU::SI_SPILL_V64_SAVE: in eliminateFrameIndex()
2033 case AMDGPU::SI_SPILL_V32_SAVE: in eliminateFrameIndex()
2034 case AMDGPU::SI_SPILL_A1024_SAVE: in eliminateFrameIndex()
2035 case AMDGPU::SI_SPILL_A512_SAVE: in eliminateFrameIndex()
2036 case AMDGPU::SI_SPILL_A256_SAVE: in eliminateFrameIndex()
2037 case AMDGPU::SI_SPILL_A224_SAVE: in eliminateFrameIndex()
2038 case AMDGPU::SI_SPILL_A192_SAVE: in eliminateFrameIndex()
2039 case AMDGPU::SI_SPILL_A160_SAVE: in eliminateFrameIndex()
2040 case AMDGPU::SI_SPILL_A128_SAVE: in eliminateFrameIndex()
2041 case AMDGPU::SI_SPILL_A96_SAVE: in eliminateFrameIndex()
2042 case AMDGPU::SI_SPILL_A64_SAVE: in eliminateFrameIndex()
2043 case AMDGPU::SI_SPILL_A32_SAVE: in eliminateFrameIndex()
2044 case AMDGPU::SI_SPILL_AV1024_SAVE: in eliminateFrameIndex()
2045 case AMDGPU::SI_SPILL_AV512_SAVE: in eliminateFrameIndex()
2046 case AMDGPU::SI_SPILL_AV256_SAVE: in eliminateFrameIndex()
2047 case AMDGPU::SI_SPILL_AV224_SAVE: in eliminateFrameIndex()
2048 case AMDGPU::SI_SPILL_AV192_SAVE: in eliminateFrameIndex()
2049 case AMDGPU::SI_SPILL_AV160_SAVE: in eliminateFrameIndex()
2050 case AMDGPU::SI_SPILL_AV128_SAVE: in eliminateFrameIndex()
2051 case AMDGPU::SI_SPILL_AV96_SAVE: in eliminateFrameIndex()
2052 case AMDGPU::SI_SPILL_AV64_SAVE: in eliminateFrameIndex()
2053 case AMDGPU::SI_SPILL_AV32_SAVE: { in eliminateFrameIndex()
2055 AMDGPU::OpName::vdata); in eliminateFrameIndex()
2056 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
2059 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in eliminateFrameIndex()
2060 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in eliminateFrameIndex()
2064 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
2070 case AMDGPU::SI_SPILL_V32_RESTORE: in eliminateFrameIndex()
2071 case AMDGPU::SI_SPILL_V64_RESTORE: in eliminateFrameIndex()
2072 case AMDGPU::SI_SPILL_V96_RESTORE: in eliminateFrameIndex()
2073 case AMDGPU::SI_SPILL_V128_RESTORE: in eliminateFrameIndex()
2074 case AMDGPU::SI_SPILL_V160_RESTORE: in eliminateFrameIndex()
2075 case AMDGPU::SI_SPILL_V192_RESTORE: in eliminateFrameIndex()
2076 case AMDGPU::SI_SPILL_V224_RESTORE: in eliminateFrameIndex()
2077 case AMDGPU::SI_SPILL_V256_RESTORE: in eliminateFrameIndex()
2078 case AMDGPU::SI_SPILL_V512_RESTORE: in eliminateFrameIndex()
2079 case AMDGPU::SI_SPILL_V1024_RESTORE: in eliminateFrameIndex()
2080 case AMDGPU::SI_SPILL_A32_RESTORE: in eliminateFrameIndex()
2081 case AMDGPU::SI_SPILL_A64_RESTORE: in eliminateFrameIndex()
2082 case AMDGPU::SI_SPILL_A96_RESTORE: in eliminateFrameIndex()
2083 case AMDGPU::SI_SPILL_A128_RESTORE: in eliminateFrameIndex()
2084 case AMDGPU::SI_SPILL_A160_RESTORE: in eliminateFrameIndex()
2085 case AMDGPU::SI_SPILL_A192_RESTORE: in eliminateFrameIndex()
2086 case AMDGPU::SI_SPILL_A224_RESTORE: in eliminateFrameIndex()
2087 case AMDGPU::SI_SPILL_A256_RESTORE: in eliminateFrameIndex()
2088 case AMDGPU::SI_SPILL_A512_RESTORE: in eliminateFrameIndex()
2089 case AMDGPU::SI_SPILL_A1024_RESTORE: in eliminateFrameIndex()
2090 case AMDGPU::SI_SPILL_AV32_RESTORE: in eliminateFrameIndex()
2091 case AMDGPU::SI_SPILL_AV64_RESTORE: in eliminateFrameIndex()
2092 case AMDGPU::SI_SPILL_AV96_RESTORE: in eliminateFrameIndex()
2093 case AMDGPU::SI_SPILL_AV128_RESTORE: in eliminateFrameIndex()
2094 case AMDGPU::SI_SPILL_AV160_RESTORE: in eliminateFrameIndex()
2095 case AMDGPU::SI_SPILL_AV192_RESTORE: in eliminateFrameIndex()
2096 case AMDGPU::SI_SPILL_AV224_RESTORE: in eliminateFrameIndex()
2097 case AMDGPU::SI_SPILL_AV256_RESTORE: in eliminateFrameIndex()
2098 case AMDGPU::SI_SPILL_AV512_RESTORE: in eliminateFrameIndex()
2099 case AMDGPU::SI_SPILL_AV1024_RESTORE: { in eliminateFrameIndex()
2101 AMDGPU::OpName::vdata); in eliminateFrameIndex()
2102 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
2105 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in eliminateFrameIndex()
2106 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in eliminateFrameIndex()
2110 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
2124 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
2125 AMDGPU::OpName::saddr)); in eliminateFrameIndex()
2135 TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in eliminateFrameIndex()
2148 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) != -1) { in eliminateFrameIndex()
2149 NewOpc = AMDGPU::getFlatScratchInstSVfromSVS(Opc); in eliminateFrameIndex()
2153 NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc); in eliminateFrameIndex()
2158 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr)); in eliminateFrameIndex()
2173 FIOp.ChangeToRegister(AMDGPU::M0, false); in eliminateFrameIndex()
2181 const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass in eliminateFrameIndex()
2182 : &AMDGPU::VGPR_32RegClass; in eliminateFrameIndex()
2189 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
2201 : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, in eliminateFrameIndex()
2216 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), TmpSReg) in eliminateFrameIndex()
2221 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2226 BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_ADD_I32), in eliminateFrameIndex()
2241 bool LiveSCC = RS->isRegUsed(AMDGPU::SCC); in eliminateFrameIndex()
2243 ? &AMDGPU::SReg_32RegClass in eliminateFrameIndex()
2244 : &AMDGPU::VGPR_32RegClass; in eliminateFrameIndex()
2245 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32 || in eliminateFrameIndex()
2246 MI->getOpcode() == AMDGPU::V_MOV_B32_e64; in eliminateFrameIndex()
2252 unsigned OpCode = IsSALU && !LiveSCC ? AMDGPU::S_LSHR_B32 in eliminateFrameIndex()
2253 : AMDGPU::V_LSHRREV_B32_e64; in eliminateFrameIndex()
2263 RS->scavengeRegister(&AMDGPU::SReg_32RegClass, Shift, 0); in eliminateFrameIndex()
2264 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), in eliminateFrameIndex()
2277 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), in eliminateFrameIndex()
2282 const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32; in eliminateFrameIndex()
2285 if (IsVOP2 || AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) { in eliminateFrameIndex()
2292 assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 && in eliminateFrameIndex()
2298 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); in eliminateFrameIndex()
2302 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg) in eliminateFrameIndex()
2318 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
2321 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg) in eliminateFrameIndex()
2324 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
2328 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg) in eliminateFrameIndex()
2335 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
2338 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg) in eliminateFrameIndex()
2356 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
2357 AMDGPU::OpName::vaddr)); in eliminateFrameIndex()
2359 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); in eliminateFrameIndex()
2362 if (FrameReg != AMDGPU::NoRegister) in eliminateFrameIndex()
2367 = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(); in eliminateFrameIndex()
2382 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
2383 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
2398 return &AMDGPU::VReg_64RegClass; in getAnyVGPRClassForBitWidth()
2400 return &AMDGPU::VReg_96RegClass; in getAnyVGPRClassForBitWidth()
2402 return &AMDGPU::VReg_128RegClass; in getAnyVGPRClassForBitWidth()
2404 return &AMDGPU::VReg_160RegClass; in getAnyVGPRClassForBitWidth()
2406 return &AMDGPU::VReg_192RegClass; in getAnyVGPRClassForBitWidth()
2408 return &AMDGPU::VReg_224RegClass; in getAnyVGPRClassForBitWidth()
2410 return &AMDGPU::VReg_256RegClass; in getAnyVGPRClassForBitWidth()
2412 return &AMDGPU::VReg_512RegClass; in getAnyVGPRClassForBitWidth()
2414 return &AMDGPU::VReg_1024RegClass; in getAnyVGPRClassForBitWidth()
2422 return &AMDGPU::VReg_64_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2424 return &AMDGPU::VReg_96_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2426 return &AMDGPU::VReg_128_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2428 return &AMDGPU::VReg_160_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2430 return &AMDGPU::VReg_192_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2432 return &AMDGPU::VReg_224_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2434 return &AMDGPU::VReg_256_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2436 return &AMDGPU::VReg_512_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2438 return &AMDGPU::VReg_1024_Align2RegClass; in getAlignedVGPRClassForBitWidth()
2446 return &AMDGPU::VReg_1RegClass; in getVGPRClassForBitWidth()
2448 return &AMDGPU::VGPR_LO16RegClass; in getVGPRClassForBitWidth()
2450 return &AMDGPU::VGPR_32RegClass; in getVGPRClassForBitWidth()
2458 return &AMDGPU::AReg_64RegClass; in getAnyAGPRClassForBitWidth()
2460 return &AMDGPU::AReg_96RegClass; in getAnyAGPRClassForBitWidth()
2462 return &AMDGPU::AReg_128RegClass; in getAnyAGPRClassForBitWidth()
2464 return &AMDGPU::AReg_160RegClass; in getAnyAGPRClassForBitWidth()
2466 return &AMDGPU::AReg_192RegClass; in getAnyAGPRClassForBitWidth()
2468 return &AMDGPU::AReg_224RegClass; in getAnyAGPRClassForBitWidth()
2470 return &AMDGPU::AReg_256RegClass; in getAnyAGPRClassForBitWidth()
2472 return &AMDGPU::AReg_512RegClass; in getAnyAGPRClassForBitWidth()
2474 return &AMDGPU::AReg_1024RegClass; in getAnyAGPRClassForBitWidth()
2482 return &AMDGPU::AReg_64_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2484 return &AMDGPU::AReg_96_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2486 return &AMDGPU::AReg_128_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2488 return &AMDGPU::AReg_160_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2490 return &AMDGPU::AReg_192_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2492 return &AMDGPU::AReg_224_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2494 return &AMDGPU::AReg_256_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2496 return &AMDGPU::AReg_512_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2498 return &AMDGPU::AReg_1024_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2506 return &AMDGPU::AGPR_LO16RegClass; in getAGPRClassForBitWidth()
2508 return &AMDGPU::AGPR_32RegClass; in getAGPRClassForBitWidth()
2516 return &AMDGPU::AV_64RegClass; in getAnyVectorSuperClassForBitWidth()
2518 return &AMDGPU::AV_96RegClass; in getAnyVectorSuperClassForBitWidth()
2520 return &AMDGPU::AV_128RegClass; in getAnyVectorSuperClassForBitWidth()
2522 return &AMDGPU::AV_160RegClass; in getAnyVectorSuperClassForBitWidth()
2524 return &AMDGPU::AV_192RegClass; in getAnyVectorSuperClassForBitWidth()
2526 return &AMDGPU::AV_224RegClass; in getAnyVectorSuperClassForBitWidth()
2528 return &AMDGPU::AV_256RegClass; in getAnyVectorSuperClassForBitWidth()
2530 return &AMDGPU::AV_512RegClass; in getAnyVectorSuperClassForBitWidth()
2532 return &AMDGPU::AV_1024RegClass; in getAnyVectorSuperClassForBitWidth()
2540 return &AMDGPU::AV_64_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2542 return &AMDGPU::AV_96_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2544 return &AMDGPU::AV_128_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2546 return &AMDGPU::AV_160_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2548 return &AMDGPU::AV_192_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2550 return &AMDGPU::AV_224_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2552 return &AMDGPU::AV_256_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2554 return &AMDGPU::AV_512_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2556 return &AMDGPU::AV_1024_Align2RegClass; in getAlignedVectorSuperClassForBitWidth()
2564 return &AMDGPU::VGPR_LO16RegClass; in getVectorSuperClassForBitWidth()
2566 return &AMDGPU::AV_32RegClass; in getVectorSuperClassForBitWidth()
2575 return &AMDGPU::SGPR_LO16RegClass; in getSGPRClassForBitWidth()
2577 return &AMDGPU::SReg_32RegClass; in getSGPRClassForBitWidth()
2579 return &AMDGPU::SReg_64RegClass; in getSGPRClassForBitWidth()
2581 return &AMDGPU::SGPR_96RegClass; in getSGPRClassForBitWidth()
2583 return &AMDGPU::SGPR_128RegClass; in getSGPRClassForBitWidth()
2585 return &AMDGPU::SGPR_160RegClass; in getSGPRClassForBitWidth()
2587 return &AMDGPU::SGPR_192RegClass; in getSGPRClassForBitWidth()
2589 return &AMDGPU::SGPR_224RegClass; in getSGPRClassForBitWidth()
2591 return &AMDGPU::SGPR_256RegClass; in getSGPRClassForBitWidth()
2593 return &AMDGPU::SGPR_512RegClass; in getSGPRClassForBitWidth()
2595 return &AMDGPU::SGPR_1024RegClass; in getSGPRClassForBitWidth()
2605 &AMDGPU::VGPR_LO16RegClass, in getPhysRegClass()
2606 &AMDGPU::VGPR_HI16RegClass, in getPhysRegClass()
2607 &AMDGPU::SReg_LO16RegClass, in getPhysRegClass()
2608 &AMDGPU::AGPR_LO16RegClass, in getPhysRegClass()
2609 &AMDGPU::VGPR_32RegClass, in getPhysRegClass()
2610 &AMDGPU::SReg_32RegClass, in getPhysRegClass()
2611 &AMDGPU::AGPR_32RegClass, in getPhysRegClass()
2612 &AMDGPU::AGPR_32RegClass, in getPhysRegClass()
2613 &AMDGPU::VReg_64_Align2RegClass, in getPhysRegClass()
2614 &AMDGPU::VReg_64RegClass, in getPhysRegClass()
2615 &AMDGPU::SReg_64RegClass, in getPhysRegClass()
2616 &AMDGPU::AReg_64_Align2RegClass, in getPhysRegClass()
2617 &AMDGPU::AReg_64RegClass, in getPhysRegClass()
2618 &AMDGPU::VReg_96_Align2RegClass, in getPhysRegClass()
2619 &AMDGPU::VReg_96RegClass, in getPhysRegClass()
2620 &AMDGPU::SReg_96RegClass, in getPhysRegClass()
2621 &AMDGPU::AReg_96_Align2RegClass, in getPhysRegClass()
2622 &AMDGPU::AReg_96RegClass, in getPhysRegClass()
2623 &AMDGPU::VReg_128_Align2RegClass, in getPhysRegClass()
2624 &AMDGPU::VReg_128RegClass, in getPhysRegClass()
2625 &AMDGPU::SReg_128RegClass, in getPhysRegClass()
2626 &AMDGPU::AReg_128_Align2RegClass, in getPhysRegClass()
2627 &AMDGPU::AReg_128RegClass, in getPhysRegClass()
2628 &AMDGPU::VReg_160_Align2RegClass, in getPhysRegClass()
2629 &AMDGPU::VReg_160RegClass, in getPhysRegClass()
2630 &AMDGPU::SReg_160RegClass, in getPhysRegClass()
2631 &AMDGPU::AReg_160_Align2RegClass, in getPhysRegClass()
2632 &AMDGPU::AReg_160RegClass, in getPhysRegClass()
2633 &AMDGPU::VReg_192_Align2RegClass, in getPhysRegClass()
2634 &AMDGPU::VReg_192RegClass, in getPhysRegClass()
2635 &AMDGPU::SReg_192RegClass, in getPhysRegClass()
2636 &AMDGPU::AReg_192_Align2RegClass, in getPhysRegClass()
2637 &AMDGPU::AReg_192RegClass, in getPhysRegClass()
2638 &AMDGPU::VReg_224_Align2RegClass, in getPhysRegClass()
2639 &AMDGPU::VReg_224RegClass, in getPhysRegClass()
2640 &AMDGPU::SReg_224RegClass, in getPhysRegClass()
2641 &AMDGPU::AReg_224_Align2RegClass, in getPhysRegClass()
2642 &AMDGPU::AReg_224RegClass, in getPhysRegClass()
2643 &AMDGPU::VReg_256_Align2RegClass, in getPhysRegClass()
2644 &AMDGPU::VReg_256RegClass, in getPhysRegClass()
2645 &AMDGPU::SReg_256RegClass, in getPhysRegClass()
2646 &AMDGPU::AReg_256_Align2RegClass, in getPhysRegClass()
2647 &AMDGPU::AReg_256RegClass, in getPhysRegClass()
2648 &AMDGPU::VReg_512_Align2RegClass, in getPhysRegClass()
2649 &AMDGPU::VReg_512RegClass, in getPhysRegClass()
2650 &AMDGPU::SReg_512RegClass, in getPhysRegClass()
2651 &AMDGPU::AReg_512_Align2RegClass, in getPhysRegClass()
2652 &AMDGPU::AReg_512RegClass, in getPhysRegClass()
2653 &AMDGPU::SReg_1024RegClass, in getPhysRegClass()
2654 &AMDGPU::VReg_1024_Align2RegClass, in getPhysRegClass()
2655 &AMDGPU::VReg_1024RegClass, in getPhysRegClass()
2656 &AMDGPU::AReg_1024_Align2RegClass, in getPhysRegClass()
2657 &AMDGPU::AReg_1024RegClass, in getPhysRegClass()
2658 &AMDGPU::SCC_CLASSRegClass, in getPhysRegClass()
2659 &AMDGPU::Pseudo_SReg_32RegClass, in getPhysRegClass()
2660 &AMDGPU::Pseudo_SReg_128RegClass, in getPhysRegClass()
2701 return &AMDGPU::SGPR_32RegClass; in getEquivalentSGPRClass()
2709 if (SubIdx == AMDGPU::NoSubRegister) in getSubRegClass()
2738 if (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST && in opCanUseInlineConstant()
2739 OpType <= AMDGPU::OPERAND_REG_INLINE_AC_LAST) in opCanUseInlineConstant()
2742 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in opCanUseInlineConstant()
2743 OpType <= AMDGPU::OPERAND_SRC_LAST; in opCanUseInlineConstant()
2772 return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST && in opCanUseLiteralConstant()
2773 OpType <= AMDGPU::OPERAND_REG_IMM_LAST; in opCanUseLiteralConstant()
2798 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC); in getRegSplitParts()
2862 case AMDGPU::VGPR_32RegClassID: in getRegPressureLimit()
2863 case AMDGPU::VGPR_LO16RegClassID: in getRegPressureLimit()
2864 case AMDGPU::VGPR_HI16RegClassID: in getRegPressureLimit()
2866 case AMDGPU::SGPR_32RegClassID: in getRegPressureLimit()
2867 case AMDGPU::SGPR_LO16RegClassID: in getRegPressureLimit()
2874 if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 || in getRegPressureSetLimit()
2875 Idx == AMDGPU::RegisterPressureSets::AGPR_32) in getRegPressureSetLimit()
2876 return getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in getRegPressureSetLimit()
2879 if (Idx == AMDGPU::RegisterPressureSets::SReg_32) in getRegPressureSetLimit()
2880 return getRegPressureLimit(&AMDGPU::SGPR_32RegClass, in getRegPressureSetLimit()
2897 return AMDGPU::SGPR30_SGPR31; in getReturnAddressReg()
2904 case AMDGPU::VGPRRegBankID: in getRegClassForSizeOnBank()
2906 case AMDGPU::VCCRegBankID: in getRegClassForSizeOnBank()
2908 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2909 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClassForSizeOnBank()
2910 case AMDGPU::SGPRRegBankID: in getRegClassForSizeOnBank()
2912 case AMDGPU::AGPRRegBankID: in getRegClassForSizeOnBank()
2933 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2937 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getExec()
2942 return ST.needsAlignedVGPRs() ? &AMDGPU::VReg_64_Align2RegClass in getVGPR64Class()
2943 : &AMDGPU::VReg_64RegClass; in getVGPR64Class()
2949 case AMDGPU::SReg_1RegClassID: in getRegClass()
2951 case AMDGPU::SReg_1_XEXECRegClassID: in getRegClass()
2952 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
2953 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClass()
3019 for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass, in get32BitRegister()
3020 AMDGPU::SReg_32RegClass, in get32BitRegister()
3021 AMDGPU::AGPR_32RegClass } ) { in get32BitRegister()
3022 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
3025 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
3026 &AMDGPU::VGPR_32RegClass)) { in get32BitRegister()
3030 return AMDGPU::NoRegister; in get32BitRegister()
3069 case AMDGPU::SGPR_NULL: in isConstantPhysReg()
3070 case AMDGPU::SGPR_NULL64: in isConstantPhysReg()
3071 case AMDGPU::SRC_SHARED_BASE: in isConstantPhysReg()
3072 case AMDGPU::SRC_PRIVATE_BASE: in isConstantPhysReg()
3073 case AMDGPU::SRC_SHARED_LIMIT: in isConstantPhysReg()
3074 case AMDGPU::SRC_PRIVATE_LIMIT: in isConstantPhysReg()
3083 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(), in getAllSGPR128()
3089 return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(), in getAllSGPR64()
3095 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()