Lines Matching refs:AMDGPU
103 namespace AMDGPU { namespace
164 return AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET; in getMultigridSyncArgImplicitArgPosition()
181 return AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET; in getHostcallImplicitArgPosition()
808 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch)) in getNumExtraSGPRs()
818 STI->getFeatureBits().test(AMDGPU::FeatureXNACK)); in getNumExtraSGPRs()
969 if (AMDGPU::isGFX90A(*STI)) { in getDefaultAmdhsaKernelDescriptor()
1714 return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv()); in isKernelCC()
1718 return STI.getFeatureBits()[AMDGPU::FeatureXNACK]; in hasXNACK()
1722 return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC]; in hasSRAMECC()
1726 …return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128… in hasMIMG_R128()
1730 return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16]; in hasGFX10A16()
1734 return STI.getFeatureBits()[AMDGPU::FeatureG16]; in hasG16()
1738 return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem] && !isCI(STI) && in hasPackedD16()
1743 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; in isSI()
1747 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; in isCI()
1751 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; in isVI()
1755 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; in isGFX9()
1775 return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; in isGFX10()
1783 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; in isGFX11()
1799 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI); in isGFX10Before1030()
1803 return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]; in isGCN3Encoding()
1807 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding]; in isGFX10_AEncoding()
1811 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]; in isGFX10_BEncoding()
1815 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts]; in hasGFX10_3Insts()
1819 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; in isGFX90A()
1823 return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]; in isGFX940()
1827 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; in hasArchitectedFlatScratch()
1831 return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts]; in hasMAIInsts()
1835 return STI.getFeatureBits()[AMDGPU::FeatureVOPD]; in hasVOPD()
1846 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()
1847 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0); in isSGPR()
1849 Reg == AMDGPU::SCC; in isSGPR()
1853 using namespace AMDGPU; \
1938 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in isSISrcOperand()
1939 OpType <= AMDGPU::OPERAND_SRC_LAST; in isSISrcOperand()
1946 case AMDGPU::OPERAND_REG_IMM_FP32: in isSISrcFPOperand()
1947 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in isSISrcFPOperand()
1948 case AMDGPU::OPERAND_REG_IMM_FP64: in isSISrcFPOperand()
1949 case AMDGPU::OPERAND_REG_IMM_FP16: in isSISrcFPOperand()
1950 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in isSISrcFPOperand()
1951 case AMDGPU::OPERAND_REG_IMM_V2FP16: in isSISrcFPOperand()
1952 case AMDGPU::OPERAND_REG_IMM_V2INT16: in isSISrcFPOperand()
1953 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in isSISrcFPOperand()
1954 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in isSISrcFPOperand()
1955 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in isSISrcFPOperand()
1956 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in isSISrcFPOperand()
1957 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in isSISrcFPOperand()
1958 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in isSISrcFPOperand()
1959 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in isSISrcFPOperand()
1960 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in isSISrcFPOperand()
1961 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in isSISrcFPOperand()
1962 case AMDGPU::OPERAND_REG_IMM_V2FP32: in isSISrcFPOperand()
1963 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in isSISrcFPOperand()
1964 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in isSISrcFPOperand()
1974 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST && in isSISrcInlinableOperand()
1975 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST; in isSISrcInlinableOperand()
1982 case AMDGPU::VGPR_LO16RegClassID: in getRegBitWidth()
1983 case AMDGPU::VGPR_HI16RegClassID: in getRegBitWidth()
1984 case AMDGPU::SGPR_LO16RegClassID: in getRegBitWidth()
1985 case AMDGPU::AGPR_LO16RegClassID: in getRegBitWidth()
1987 case AMDGPU::SGPR_32RegClassID: in getRegBitWidth()
1988 case AMDGPU::VGPR_32RegClassID: in getRegBitWidth()
1989 case AMDGPU::VRegOrLds_32RegClassID: in getRegBitWidth()
1990 case AMDGPU::AGPR_32RegClassID: in getRegBitWidth()
1991 case AMDGPU::VS_32RegClassID: in getRegBitWidth()
1992 case AMDGPU::AV_32RegClassID: in getRegBitWidth()
1993 case AMDGPU::SReg_32RegClassID: in getRegBitWidth()
1994 case AMDGPU::SReg_32_XM0RegClassID: in getRegBitWidth()
1995 case AMDGPU::SRegOrLds_32RegClassID: in getRegBitWidth()
1997 case AMDGPU::SGPR_64RegClassID: in getRegBitWidth()
1998 case AMDGPU::VS_64RegClassID: in getRegBitWidth()
1999 case AMDGPU::SReg_64RegClassID: in getRegBitWidth()
2000 case AMDGPU::VReg_64RegClassID: in getRegBitWidth()
2001 case AMDGPU::AReg_64RegClassID: in getRegBitWidth()
2002 case AMDGPU::SReg_64_XEXECRegClassID: in getRegBitWidth()
2003 case AMDGPU::VReg_64_Align2RegClassID: in getRegBitWidth()
2004 case AMDGPU::AReg_64_Align2RegClassID: in getRegBitWidth()
2005 case AMDGPU::AV_64RegClassID: in getRegBitWidth()
2006 case AMDGPU::AV_64_Align2RegClassID: in getRegBitWidth()
2008 case AMDGPU::SGPR_96RegClassID: in getRegBitWidth()
2009 case AMDGPU::SReg_96RegClassID: in getRegBitWidth()
2010 case AMDGPU::VReg_96RegClassID: in getRegBitWidth()
2011 case AMDGPU::AReg_96RegClassID: in getRegBitWidth()
2012 case AMDGPU::VReg_96_Align2RegClassID: in getRegBitWidth()
2013 case AMDGPU::AReg_96_Align2RegClassID: in getRegBitWidth()
2014 case AMDGPU::AV_96RegClassID: in getRegBitWidth()
2015 case AMDGPU::AV_96_Align2RegClassID: in getRegBitWidth()
2017 case AMDGPU::SGPR_128RegClassID: in getRegBitWidth()
2018 case AMDGPU::SReg_128RegClassID: in getRegBitWidth()
2019 case AMDGPU::VReg_128RegClassID: in getRegBitWidth()
2020 case AMDGPU::AReg_128RegClassID: in getRegBitWidth()
2021 case AMDGPU::VReg_128_Align2RegClassID: in getRegBitWidth()
2022 case AMDGPU::AReg_128_Align2RegClassID: in getRegBitWidth()
2023 case AMDGPU::AV_128RegClassID: in getRegBitWidth()
2024 case AMDGPU::AV_128_Align2RegClassID: in getRegBitWidth()
2026 case AMDGPU::SGPR_160RegClassID: in getRegBitWidth()
2027 case AMDGPU::SReg_160RegClassID: in getRegBitWidth()
2028 case AMDGPU::VReg_160RegClassID: in getRegBitWidth()
2029 case AMDGPU::AReg_160RegClassID: in getRegBitWidth()
2030 case AMDGPU::VReg_160_Align2RegClassID: in getRegBitWidth()
2031 case AMDGPU::AReg_160_Align2RegClassID: in getRegBitWidth()
2032 case AMDGPU::AV_160RegClassID: in getRegBitWidth()
2033 case AMDGPU::AV_160_Align2RegClassID: in getRegBitWidth()
2035 case AMDGPU::SGPR_192RegClassID: in getRegBitWidth()
2036 case AMDGPU::SReg_192RegClassID: in getRegBitWidth()
2037 case AMDGPU::VReg_192RegClassID: in getRegBitWidth()
2038 case AMDGPU::AReg_192RegClassID: in getRegBitWidth()
2039 case AMDGPU::VReg_192_Align2RegClassID: in getRegBitWidth()
2040 case AMDGPU::AReg_192_Align2RegClassID: in getRegBitWidth()
2041 case AMDGPU::AV_192RegClassID: in getRegBitWidth()
2042 case AMDGPU::AV_192_Align2RegClassID: in getRegBitWidth()
2044 case AMDGPU::SGPR_224RegClassID: in getRegBitWidth()
2045 case AMDGPU::SReg_224RegClassID: in getRegBitWidth()
2046 case AMDGPU::VReg_224RegClassID: in getRegBitWidth()
2047 case AMDGPU::AReg_224RegClassID: in getRegBitWidth()
2048 case AMDGPU::VReg_224_Align2RegClassID: in getRegBitWidth()
2049 case AMDGPU::AReg_224_Align2RegClassID: in getRegBitWidth()
2050 case AMDGPU::AV_224RegClassID: in getRegBitWidth()
2051 case AMDGPU::AV_224_Align2RegClassID: in getRegBitWidth()
2053 case AMDGPU::SGPR_256RegClassID: in getRegBitWidth()
2054 case AMDGPU::SReg_256RegClassID: in getRegBitWidth()
2055 case AMDGPU::VReg_256RegClassID: in getRegBitWidth()
2056 case AMDGPU::AReg_256RegClassID: in getRegBitWidth()
2057 case AMDGPU::VReg_256_Align2RegClassID: in getRegBitWidth()
2058 case AMDGPU::AReg_256_Align2RegClassID: in getRegBitWidth()
2059 case AMDGPU::AV_256RegClassID: in getRegBitWidth()
2060 case AMDGPU::AV_256_Align2RegClassID: in getRegBitWidth()
2062 case AMDGPU::SGPR_512RegClassID: in getRegBitWidth()
2063 case AMDGPU::SReg_512RegClassID: in getRegBitWidth()
2064 case AMDGPU::VReg_512RegClassID: in getRegBitWidth()
2065 case AMDGPU::AReg_512RegClassID: in getRegBitWidth()
2066 case AMDGPU::VReg_512_Align2RegClassID: in getRegBitWidth()
2067 case AMDGPU::AReg_512_Align2RegClassID: in getRegBitWidth()
2068 case AMDGPU::AV_512RegClassID: in getRegBitWidth()
2069 case AMDGPU::AV_512_Align2RegClassID: in getRegBitWidth()
2071 case AMDGPU::SGPR_1024RegClassID: in getRegBitWidth()
2072 case AMDGPU::SReg_1024RegClassID: in getRegBitWidth()
2073 case AMDGPU::VReg_1024RegClassID: in getRegBitWidth()
2074 case AMDGPU::AReg_1024RegClassID: in getRegBitWidth()
2075 case AMDGPU::VReg_1024_Align2RegClassID: in getRegBitWidth()
2076 case AMDGPU::AReg_1024_Align2RegClassID: in getRegBitWidth()
2077 case AMDGPU::AV_1024RegClassID: in getRegBitWidth()
2078 case AMDGPU::AV_1024_Align2RegClassID: in getRegBitWidth()
2163 return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi); in isInlinableLiteralV216()
2166 return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi); in isInlinableLiteralV216()
2287 if (AMDGPU::isGFX10(ST)) in getNumFlatOffsetBits()
2414 const AMDGPU::IsaInfo::TargetIDSetting S) { in operator <<()
2416 case (AMDGPU::IsaInfo::TargetIDSetting::Unsupported): in operator <<()
2419 case (AMDGPU::IsaInfo::TargetIDSetting::Any): in operator <<()
2422 case (AMDGPU::IsaInfo::TargetIDSetting::Off): in operator <<()
2425 case (AMDGPU::IsaInfo::TargetIDSetting::On): in operator <<()