Lines Matching refs:AMDGPU
126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
135 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
136 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
137 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
138 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
146 int DPP32 = AMDGPU::getDPPOp32(Op); in getDPPOp()
149 int E32 = AMDGPU::getVOPe32(Op); in getDPPOp()
150 DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32); in getDPPOp()
156 DPP64 = AMDGPU::getDPPOp64(Op); in getDPPOp()
173 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
175 case AMDGPU::COPY: in getOldOpndValue()
176 case AMDGPU::V_MOV_B32_e32: in getOldOpndValue()
177 case AMDGPU::V_MOV_B64_PSEUDO: in getOldOpndValue()
178 case AMDGPU::V_MOV_B64_e32: in getOldOpndValue()
179 case AMDGPU::V_MOV_B64_e64: { in getOldOpndValue()
194 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in createDPPInst()
195 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in createDPPInst()
196 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in createDPPInst()
205 int OrigOpE32 = AMDGPU::getVOPe32(OrigOp); in createDPPInst()
207 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
209 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
226 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
230 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
238 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
244 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
263 AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
264 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
265 AMDGPU::OpName::src0_modifiers)); in createDPPInst()
270 } else if (AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
271 AMDGPU::OpName::src0_modifiers) != -1) { in createDPPInst()
275 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
287 AMDGPU::OpName::src1_modifiers)) { in createDPPInst()
288 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
289 AMDGPU::OpName::src1_modifiers)); in createDPPInst()
294 } else if (AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
295 AMDGPU::OpName::src1_modifiers) != -1) { in createDPPInst()
299 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
310 TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) { in createDPPInst()
312 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers)); in createDPPInst()
318 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
320 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
330 auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); in createDPPInst()
332 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::clamp) != -1) { in createDPPInst()
335 auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in); in createDPPInst()
337 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::vdst_in) != -1) { in createDPPInst()
340 auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod); in createDPPInst()
342 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::omod) != -1) { in createDPPInst()
348 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { in createDPPInst()
355 if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel) != -1) in createDPPInst()
359 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { in createDPPInst()
369 if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel_hi) != -1) in createDPPInst()
372 auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo); in createDPPInst()
374 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_lo) != -1) { in createDPPInst()
377 auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi); in createDPPInst()
379 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_hi) != -1) { in createDPPInst()
383 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
384 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); in createDPPInst()
385 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); in createDPPInst()
401 case AMDGPU::V_ADD_U32_e32: in isIdentityValue()
402 case AMDGPU::V_ADD_U32_e64: in isIdentityValue()
403 case AMDGPU::V_ADD_CO_U32_e32: in isIdentityValue()
404 case AMDGPU::V_ADD_CO_U32_e64: in isIdentityValue()
405 case AMDGPU::V_OR_B32_e32: in isIdentityValue()
406 case AMDGPU::V_OR_B32_e64: in isIdentityValue()
407 case AMDGPU::V_SUBREV_U32_e32: in isIdentityValue()
408 case AMDGPU::V_SUBREV_U32_e64: in isIdentityValue()
409 case AMDGPU::V_SUBREV_CO_U32_e32: in isIdentityValue()
410 case AMDGPU::V_SUBREV_CO_U32_e64: in isIdentityValue()
411 case AMDGPU::V_MAX_U32_e32: in isIdentityValue()
412 case AMDGPU::V_MAX_U32_e64: in isIdentityValue()
413 case AMDGPU::V_XOR_B32_e32: in isIdentityValue()
414 case AMDGPU::V_XOR_B32_e64: in isIdentityValue()
418 case AMDGPU::V_AND_B32_e32: in isIdentityValue()
419 case AMDGPU::V_AND_B32_e64: in isIdentityValue()
420 case AMDGPU::V_MIN_U32_e32: in isIdentityValue()
421 case AMDGPU::V_MIN_U32_e64: in isIdentityValue()
426 case AMDGPU::V_MIN_I32_e32: in isIdentityValue()
427 case AMDGPU::V_MIN_I32_e64: in isIdentityValue()
432 case AMDGPU::V_MAX_I32_e32: in isIdentityValue()
433 case AMDGPU::V_MAX_I32_e64: in isIdentityValue()
438 case AMDGPU::V_MUL_I32_I24_e32: in isIdentityValue()
439 case AMDGPU::V_MUL_I32_I24_e64: in isIdentityValue()
440 case AMDGPU::V_MUL_U32_U24_e32: in isIdentityValue()
441 case AMDGPU::V_MUL_U32_U24_e64: in isIdentityValue()
454 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
464 auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in createDPPInst()
487 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in combineDPPMov()
488 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in combineDPPMov()
489 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in combineDPPMov()
492 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
505 if (MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in combineDPPMov()
506 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in combineDPPMov()
507 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov()
509 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) { in combineDPPMov()
517 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in combineDPPMov()
519 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in combineDPPMov()
524 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl); in combineDPPMov()
528 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old); in combineDPPMov()
529 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in combineDPPMov()
583 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg); in combineDPPMov()
603 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()
641 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
646 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov()
647 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov()
653 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov()
725 if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) { in runOnMachineFunction()
728 } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in runOnMachineFunction()
729 MI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in runOnMachineFunction()