Lines Matching refs:AMDGPU
2 …mdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU
4 …le-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefixes=AMDGPU-DISABLED
844 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
845 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
846 ; AMDGPU-SAME: () #[[ATTR0:[0-9]+]] {
847 ; AMDGPU-NEXT: entry:
848 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
849 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
850 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i…
851 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
852 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
853 ; AMDGPU: user_code.entry:
854 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
855 ; AMDGPU-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[…
856 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
857 ; AMDGPU-NEXT: ret void
858 ; AMDGPU: worker.exit:
859 ; AMDGPU-NEXT: ret void
862 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
863 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__
864 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
865 ; AMDGPU-NEXT: entry:
866 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
867 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
868 ; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8:[0-9]+]]
869 ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR9:[0-9]+]]
870 ; AMDGPU-NEXT: ret void
873 ; AMDGPU: Function Attrs: convergent noinline nounwind
874 ; AMDGPU-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
875 ; AMDGPU-SAME: () #[[ATTR1:[0-9]+]] {
876 ; AMDGPU-NEXT: entry:
877 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]…
878 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])…
879 ; AMDGPU-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
880 ; AMDGPU-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
881 ; AMDGPU: omp_if.then:
882 ; AMDGPU-NEXT: store i32 0, i32* @G, align 4
883 ; AMDGPU-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
884 ; AMDGPU-NEXT: br label [[OMP_IF_END]]
885 ; AMDGPU: omp_if.end:
886 ; AMDGPU-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) #[[AT…
887 ; AMDGPU-NEXT: ret void
890 ; AMDGPU: Function Attrs: convergent noinline nounwind
891 ; AMDGPU-LABEL: define {{[^@]+}}@no_parallel_region_in_here
892 ; AMDGPU-SAME: () #[[ATTR1]] {
893 ; AMDGPU-NEXT: entry:
894 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
895 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
896 ; AMDGPU-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
897 ; AMDGPU-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
898 ; AMDGPU: omp_if.then:
899 ; AMDGPU-NEXT: store i32 0, i32* @G, align 4
900 ; AMDGPU-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
901 ; AMDGPU-NEXT: br label [[OMP_IF_END]]
902 ; AMDGPU: omp_if.end:
903 ; AMDGPU-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
904 ; AMDGPU-NEXT: ret void
907 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
908 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
909 ; AMDGPU-SAME: () #[[ATTR0]] {
910 ; AMDGPU-NEXT: entry:
911 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
912 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
913 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
914 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
915 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
916 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
917 ; AMDGPU: is_worker_check:
918 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
919 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
920 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
921 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
922 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
923 ; AMDGPU: worker_state_machine.begin:
924 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
925 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
926 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
927 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
928 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
929 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
930 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
931 ; AMDGPU: worker_state_machine.finished:
932 ; AMDGPU-NEXT: ret void
933 ; AMDGPU: worker_state_machine.is_active.check:
934 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
935 ; AMDGPU: worker_state_machine.parallel_region.check:
936 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
937 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
938 ; AMDGPU: worker_state_machine.parallel_region.execute:
939 ; AMDGPU-NEXT: call void @__omp_outlined__2_wrapper(i16 0, i32 [[TMP0]])
940 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
941 ; AMDGPU: worker_state_machine.parallel_region.check1:
942 ; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[…
943 ; AMDGPU: worker_state_machine.parallel_region.execute2:
944 ; AMDGPU-NEXT: call void @__omp_outlined__3_wrapper(i16 0, i32 [[TMP0]])
945 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
946 ; AMDGPU: worker_state_machine.parallel_region.check3:
947 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
948 ; AMDGPU: worker_state_machine.parallel_region.end:
949 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
950 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
951 ; AMDGPU: worker_state_machine.done.barrier:
952 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
953 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
954 ; AMDGPU: thread.user_code.check:
955 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
956 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
957 ; AMDGPU: user_code.entry:
958 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
959 ; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
960 ; AMDGPU-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #…
961 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
962 ; AMDGPU-NEXT: ret void
963 ; AMDGPU: worker.exit:
964 ; AMDGPU-NEXT: ret void
967 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
968 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__1
969 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
970 ; AMDGPU-NEXT: entry:
971 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
972 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
973 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
974 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
975 ; AMDGPU-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
976 ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
977 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
978 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
979 ; AMDGPU-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
980 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
981 ; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
982 ; AMDGPU-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
983 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
984 ; AMDGPU-NEXT: ret void
987 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
988 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2
989 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
990 ; AMDGPU-NEXT: entry:
991 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
992 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
993 ; AMDGPU-NEXT: call void @p0() #[[ATTR10:[0-9]+]]
994 ; AMDGPU-NEXT: ret void
997 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
998 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
999 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1000 ; AMDGPU-NEXT: entry:
1001 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1002 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1003 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1004 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1005 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1006 ; AMDGPU-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1007 ; AMDGPU-NEXT: ret void
1010 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1011 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3
1012 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1013 ; AMDGPU-NEXT: entry:
1014 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1015 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1016 ; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
1017 ; AMDGPU-NEXT: ret void
1020 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1021 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
1022 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1023 ; AMDGPU-NEXT: entry:
1024 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1025 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1026 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1027 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1028 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1029 ; AMDGPU-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1030 ; AMDGPU-NEXT: ret void
1033 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1034 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l…
1035 ; AMDGPU-SAME: () #[[ATTR0]] {
1036 ; AMDGPU-NEXT: entry:
1037 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1038 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1039 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1040 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1041 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1042 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1043 ; AMDGPU: is_worker_check:
1044 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1045 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1046 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1047 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1048 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1049 ; AMDGPU: worker_state_machine.begin:
1050 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1051 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1052 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1053 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1054 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1055 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1056 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1057 ; AMDGPU: worker_state_machine.finished:
1058 ; AMDGPU-NEXT: ret void
1059 ; AMDGPU: worker_state_machine.is_active.check:
1060 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
1061 ; AMDGPU: worker_state_machine.parallel_region.check:
1062 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
1063 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
1064 ; AMDGPU: worker_state_machine.parallel_region.execute:
1065 ; AMDGPU-NEXT: call void @__omp_outlined__17_wrapper(i16 0, i32 [[TMP0]])
1066 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1067 ; AMDGPU: worker_state_machine.parallel_region.check1:
1068 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN…
1069 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_RE…
1070 ; AMDGPU: worker_state_machine.parallel_region.execute2:
1071 ; AMDGPU-NEXT: call void @__omp_outlined__5_wrapper(i16 0, i32 [[TMP0]])
1072 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1073 ; AMDGPU: worker_state_machine.parallel_region.check3:
1074 ; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE5:%.*]], label [[…
1075 ; AMDGPU: worker_state_machine.parallel_region.execute5:
1076 ; AMDGPU-NEXT: call void @__omp_outlined__18_wrapper(i16 0, i32 [[TMP0]])
1077 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1078 ; AMDGPU: worker_state_machine.parallel_region.check6:
1079 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1080 ; AMDGPU: worker_state_machine.parallel_region.end:
1081 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1082 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1083 ; AMDGPU: worker_state_machine.done.barrier:
1084 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1085 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1086 ; AMDGPU: thread.user_code.check:
1087 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1088 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1089 ; AMDGPU: user_code.entry:
1090 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1091 ; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
1092 ; AMDGPU-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #…
1093 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1094 ; AMDGPU-NEXT: ret void
1095 ; AMDGPU: worker.exit:
1096 ; AMDGPU-NEXT: ret void
1099 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1100 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__4
1101 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1102 ; AMDGPU-NEXT: entry:
1103 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1104 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1105 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1106 ; AMDGPU-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1107 ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
1108 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR8]]
1109 ; AMDGPU-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
1110 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1111 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1112 ; AMDGPU-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1113 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1114 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR8]]
1115 ; AMDGPU-NEXT: ret void
1118 ; AMDGPU: Function Attrs: convergent noinline nounwind
1119 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
1120 ; AMDGPU-SAME: () #[[ATTR1]] {
1121 ; AMDGPU-NEXT: entry:
1122 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1123 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) #[…
1124 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1125 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1126 ; AMDGPU-NEXT: ret void
1129 ; AMDGPU: Function Attrs: convergent noinline nounwind
1130 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
1131 ; AMDGPU-SAME: () #[[ATTR1]] {
1132 ; AMDGPU-NEXT: entry:
1133 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1134 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
1135 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1136 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1137 ; AMDGPU-NEXT: ret void
1140 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1141 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5
1142 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1143 ; AMDGPU-NEXT: entry:
1144 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1145 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1146 ; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
1147 ; AMDGPU-NEXT: ret void
1150 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1151 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
1152 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1153 ; AMDGPU-NEXT: entry:
1154 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1155 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1156 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1157 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1158 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1159 ; AMDGPU-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1160 ; AMDGPU-NEXT: ret void
1163 ; AMDGPU: Function Attrs: convergent noinline nounwind
1164 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
1165 ; AMDGPU-SAME: () #[[ATTR1]] {
1166 ; AMDGPU-NEXT: entry:
1167 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1168 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) #[…
1169 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1170 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1171 ; AMDGPU-NEXT: ret void
1174 ; AMDGPU: Function Attrs: convergent noinline nounwind
1175 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
1176 ; AMDGPU-SAME: () #[[ATTR1]] {
1177 ; AMDGPU-NEXT: entry:
1178 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1179 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
1180 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1181 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1182 ; AMDGPU-NEXT: ret void
1185 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1186 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
1187 ; AMDGPU-SAME: () #[[ATTR0]] {
1188 ; AMDGPU-NEXT: entry:
1189 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1190 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1191 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1192 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1193 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1194 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1195 ; AMDGPU: is_worker_check:
1196 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1197 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1198 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1199 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1200 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1201 ; AMDGPU: worker_state_machine.begin:
1202 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1203 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1204 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1205 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1206 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1207 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1208 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1209 ; AMDGPU: worker_state_machine.finished:
1210 ; AMDGPU-NEXT: ret void
1211 ; AMDGPU: worker_state_machine.is_active.check:
1212 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
1213 ; AMDGPU: worker_state_machine.parallel_region.check:
1214 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
1215 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
1216 ; AMDGPU: worker_state_machine.parallel_region.execute:
1217 ; AMDGPU-NEXT: call void @__omp_outlined__7_wrapper(i16 0, i32 [[TMP0]])
1218 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1219 ; AMDGPU: worker_state_machine.parallel_region.check1:
1220 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION4:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN…
1221 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION4]], label [[WORKER_STATE_MACHINE_PARALLEL_RE…
1222 ; AMDGPU: worker_state_machine.parallel_region.execute2:
1223 ; AMDGPU-NEXT: call void @__omp_outlined__8_wrapper(i16 0, i32 [[TMP0]])
1224 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1225 ; AMDGPU: worker_state_machine.parallel_region.fallback.execute:
1226 ; AMDGPU-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
1227 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1228 ; AMDGPU: worker_state_machine.parallel_region.end:
1229 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1230 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1231 ; AMDGPU: worker_state_machine.done.barrier:
1232 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1233 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1234 ; AMDGPU: thread.user_code.check:
1235 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1236 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1237 ; AMDGPU: user_code.entry:
1238 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1239 ; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
1240 ; AMDGPU-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #…
1241 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1242 ; AMDGPU-NEXT: ret void
1243 ; AMDGPU: worker.exit:
1244 ; AMDGPU-NEXT: ret void
1247 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1248 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__6
1249 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1250 ; AMDGPU-NEXT: entry:
1251 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1252 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1253 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1254 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
1255 ; AMDGPU-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1256 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1257 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1258 ; AMDGPU-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1259 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1260 ; AMDGPU-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR10]]
1261 ; AMDGPU-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
1262 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1263 ; AMDGPU-NEXT: ret void
1266 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1267 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7
1268 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1269 ; AMDGPU-NEXT: entry:
1270 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1271 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1272 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1273 ; AMDGPU-NEXT: ret void
1276 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1277 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
1278 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1279 ; AMDGPU-NEXT: entry:
1280 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1281 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1282 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1283 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1284 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1285 ; AMDGPU-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1286 ; AMDGPU-NEXT: ret void
1289 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1290 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8
1291 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1292 ; AMDGPU-NEXT: entry:
1293 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1294 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1295 ; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
1296 ; AMDGPU-NEXT: ret void
1299 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1300 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
1301 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1302 ; AMDGPU-NEXT: entry:
1303 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1304 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1305 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1306 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1307 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1308 ; AMDGPU-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1309 ; AMDGPU-NEXT: ret void
1312 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1313 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
1314 ; AMDGPU-SAME: () #[[ATTR0]] {
1315 ; AMDGPU-NEXT: entry:
1316 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1317 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1318 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1319 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1320 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1321 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1322 ; AMDGPU: is_worker_check:
1323 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1324 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1325 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1326 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1327 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1328 ; AMDGPU: worker_state_machine.begin:
1329 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1330 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1331 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1332 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1333 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1334 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1335 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1336 ; AMDGPU: worker_state_machine.finished:
1337 ; AMDGPU-NEXT: ret void
1338 ; AMDGPU: worker_state_machine.is_active.check:
1339 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
1340 ; AMDGPU: worker_state_machine.parallel_region.check:
1341 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
1342 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
1343 ; AMDGPU: worker_state_machine.parallel_region.execute:
1344 ; AMDGPU-NEXT: call void @__omp_outlined__10_wrapper(i16 0, i32 [[TMP0]])
1345 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1346 ; AMDGPU: worker_state_machine.parallel_region.check1:
1347 ; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[…
1348 ; AMDGPU: worker_state_machine.parallel_region.execute2:
1349 ; AMDGPU-NEXT: call void @__omp_outlined__11_wrapper(i16 0, i32 [[TMP0]])
1350 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1351 ; AMDGPU: worker_state_machine.parallel_region.check3:
1352 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1353 ; AMDGPU: worker_state_machine.parallel_region.end:
1354 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1355 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1356 ; AMDGPU: worker_state_machine.done.barrier:
1357 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1358 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1359 ; AMDGPU: thread.user_code.check:
1360 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1361 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1362 ; AMDGPU: user_code.entry:
1363 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1364 ; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
1365 ; AMDGPU-NEXT: call void @__omp_outlined__9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #…
1366 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1367 ; AMDGPU-NEXT: ret void
1368 ; AMDGPU: worker.exit:
1369 ; AMDGPU-NEXT: ret void
1372 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1373 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__9
1374 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1375 ; AMDGPU-NEXT: entry:
1376 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1377 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1378 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1379 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
1380 ; AMDGPU-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1381 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1382 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1383 ; AMDGPU-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1384 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1385 ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
1386 ; AMDGPU-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
1387 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1388 ; AMDGPU-NEXT: ret void
1391 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1392 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10
1393 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1394 ; AMDGPU-NEXT: entry:
1395 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1396 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1397 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1398 ; AMDGPU-NEXT: ret void
1401 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1402 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
1403 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1404 ; AMDGPU-NEXT: entry:
1405 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1406 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1407 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1408 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1409 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1410 ; AMDGPU-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1411 ; AMDGPU-NEXT: ret void
1414 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1415 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11
1416 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1417 ; AMDGPU-NEXT: entry:
1418 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1419 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1420 ; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
1421 ; AMDGPU-NEXT: ret void
1424 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1425 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
1426 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1427 ; AMDGPU-NEXT: entry:
1428 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1429 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1430 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1431 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1432 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1433 ; AMDGPU-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1434 ; AMDGPU-NEXT: ret void
1437 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1438 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
1439 ; AMDGPU-SAME: () #[[ATTR0]] {
1440 ; AMDGPU-NEXT: entry:
1441 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1442 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1443 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1444 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1445 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1446 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1447 ; AMDGPU: is_worker_check:
1448 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1449 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1450 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1451 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1452 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1453 ; AMDGPU: worker_state_machine.begin:
1454 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1455 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1456 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1457 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1458 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1459 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1460 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1461 ; AMDGPU: worker_state_machine.finished:
1462 ; AMDGPU-NEXT: ret void
1463 ; AMDGPU: worker_state_machine.is_active.check:
1464 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
1465 ; AMDGPU: worker_state_machine.parallel_region.check:
1466 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
1467 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
1468 ; AMDGPU: worker_state_machine.parallel_region.execute:
1469 ; AMDGPU-NEXT: call void @__omp_outlined__13_wrapper(i16 0, i32 [[TMP0]])
1470 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1471 ; AMDGPU: worker_state_machine.parallel_region.check1:
1472 ; AMDGPU-NEXT: br i1 true, label [[WORKER_STATE_MACHINE_PARALLEL_REGION_EXECUTE2:%.*]], label [[…
1473 ; AMDGPU: worker_state_machine.parallel_region.execute2:
1474 ; AMDGPU-NEXT: call void @__omp_outlined__14_wrapper(i16 0, i32 [[TMP0]])
1475 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1476 ; AMDGPU: worker_state_machine.parallel_region.check3:
1477 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1478 ; AMDGPU: worker_state_machine.parallel_region.end:
1479 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1480 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1481 ; AMDGPU: worker_state_machine.done.barrier:
1482 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1483 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1484 ; AMDGPU: thread.user_code.check:
1485 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1486 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1487 ; AMDGPU: user_code.entry:
1488 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1489 ; AMDGPU-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
1490 ; AMDGPU-NEXT: call void @__omp_outlined__12(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) …
1491 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1492 ; AMDGPU-NEXT: ret void
1493 ; AMDGPU: worker.exit:
1494 ; AMDGPU-NEXT: ret void
1497 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1498 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__12
1499 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1500 ; AMDGPU-NEXT: entry:
1501 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1502 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1503 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1504 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
1505 ; AMDGPU-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1506 ; AMDGPU-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
1507 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1508 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1509 ; AMDGPU-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1510 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1511 ; AMDGPU-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
1512 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i…
1513 ; AMDGPU-NEXT: ret void
1516 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1517 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13
1518 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1519 ; AMDGPU-NEXT: entry:
1520 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1521 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1522 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1523 ; AMDGPU-NEXT: ret void
1526 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1527 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
1528 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1529 ; AMDGPU-NEXT: entry:
1530 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1531 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1532 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1533 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1534 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1535 ; AMDGPU-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1536 ; AMDGPU-NEXT: ret void
1539 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1540 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14
1541 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1542 ; AMDGPU-NEXT: entry:
1543 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1544 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1545 ; AMDGPU-NEXT: call void @p1() #[[ATTR10]]
1546 ; AMDGPU-NEXT: ret void
1549 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1550 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
1551 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1552 ; AMDGPU-NEXT: entry:
1553 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1554 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1555 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1556 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1557 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1558 ; AMDGPU-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1559 ; AMDGPU-NEXT: ret void
1562 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1563 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_n…
1564 ; AMDGPU-SAME: () #[[ATTR0]] {
1565 ; AMDGPU-NEXT: entry:
1566 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1567 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1568 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1569 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1570 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1571 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1572 ; AMDGPU: is_worker_check:
1573 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1574 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1575 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1576 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1577 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1578 ; AMDGPU: worker_state_machine.begin:
1579 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1580 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1581 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1582 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1583 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1584 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1585 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1586 ; AMDGPU: worker_state_machine.finished:
1587 ; AMDGPU-NEXT: ret void
1588 ; AMDGPU: worker_state_machine.is_active.check:
1589 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_CHECK:%.…
1590 ; AMDGPU: worker_state_machine.parallel_region.check:
1591 ; AMDGPU-NEXT: [[WORKER_CHECK_PARALLEL_REGION:%.*]] = icmp eq void (i16, i32)* [[WORKER_WORK_FN_…
1592 ; AMDGPU-NEXT: br i1 [[WORKER_CHECK_PARALLEL_REGION]], label [[WORKER_STATE_MACHINE_PARALLEL_REG…
1593 ; AMDGPU: worker_state_machine.parallel_region.execute:
1594 ; AMDGPU-NEXT: call void @__omp_outlined__19_wrapper(i16 0, i32 [[TMP0]])
1595 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1596 ; AMDGPU: worker_state_machine.parallel_region.fallback.execute:
1597 ; AMDGPU-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
1598 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END]]
1599 ; AMDGPU: worker_state_machine.parallel_region.end:
1600 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1601 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1602 ; AMDGPU: worker_state_machine.done.barrier:
1603 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1604 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1605 ; AMDGPU: thread.user_code.check:
1606 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1607 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1608 ; AMDGPU: user_code.entry:
1609 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1610 ; AMDGPU-NEXT: call void @__omp_outlined__15(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) …
1611 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1612 ; AMDGPU-NEXT: ret void
1613 ; AMDGPU: worker.exit:
1614 ; AMDGPU-NEXT: ret void
1617 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1618 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__15
1619 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1620 ; AMDGPU-NEXT: entry:
1621 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1622 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1623 ; AMDGPU-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @omp_get_thread_num to i32 ()*)() #[[…
1624 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internaliz…
1625 ; AMDGPU-NEXT: ret void
1628 ; AMDGPU: Function Attrs: convergent noinline nounwind
1629 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.intern…
1630 ; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
1631 ; AMDGPU-NEXT: entry:
1632 ; AMDGPU-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1633 ; AMDGPU-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1634 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1635 ; AMDGPU-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
1636 ; AMDGPU-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
1637 ; AMDGPU: if.then:
1638 ; AMDGPU-NEXT: br label [[RETURN:%.*]]
1639 ; AMDGPU: if.end:
1640 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
1641 ; AMDGPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
1642 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.internaliz…
1643 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after.inte…
1644 ; AMDGPU-NEXT: br label [[RETURN]]
1645 ; AMDGPU: return:
1646 ; AMDGPU-NEXT: ret void
1649 ; AMDGPU: Function Attrs: convergent noinline nounwind
1650 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
1651 ; AMDGPU-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
1652 ; AMDGPU-NEXT: entry:
1653 ; AMDGPU-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1654 ; AMDGPU-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1655 ; AMDGPU-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1656 ; AMDGPU-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
1657 ; AMDGPU-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
1658 ; AMDGPU: if.then:
1659 ; AMDGPU-NEXT: br label [[RETURN:%.*]]
1660 ; AMDGPU: if.end:
1661 ; AMDGPU-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
1662 ; AMDGPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
1663 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]…
1664 ; AMDGPU-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[…
1665 ; AMDGPU-NEXT: br label [[RETURN]]
1666 ; AMDGPU: return:
1667 ; AMDGPU-NEXT: ret void
1670 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1671 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
1672 ; AMDGPU-SAME: () #[[ATTR0]] {
1673 ; AMDGPU-NEXT: entry:
1674 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR:%.*]] = alloca i8*, align 8, addrspace(5)
1675 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1676 ; AMDGPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1677 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]], i8 1, i1…
1678 ; AMDGPU-NEXT: [[THREAD_IS_WORKER:%.*]] = icmp ne i32 [[TMP0]], -1
1679 ; AMDGPU-NEXT: br i1 [[THREAD_IS_WORKER]], label [[IS_WORKER_CHECK:%.*]], label [[THREAD_USER_CO…
1680 ; AMDGPU: is_worker_check:
1681 ; AMDGPU-NEXT: [[BLOCK_HW_SIZE:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1682 ; AMDGPU-NEXT: [[WARP_SIZE:%.*]] = call i32 @__kmpc_get_warp_size()
1683 ; AMDGPU-NEXT: [[BLOCK_SIZE:%.*]] = sub i32 [[BLOCK_HW_SIZE]], [[WARP_SIZE]]
1684 ; AMDGPU-NEXT: [[THREAD_IS_MAIN_OR_WORKER:%.*]] = icmp slt i32 [[TMP0]], [[BLOCK_SIZE]]
1685 ; AMDGPU-NEXT: br i1 [[THREAD_IS_MAIN_OR_WORKER]], label [[WORKER_STATE_MACHINE_BEGIN:%.*]], lab…
1686 ; AMDGPU: worker_state_machine.begin:
1687 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1688 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_GENERIC:%.*]] = addrspacecast i8* addrspace(5)* [[WORKER_WO…
1689 ; AMDGPU-NEXT: [[WORKER_IS_ACTIVE:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORKER_WORK_FN_…
1690 ; AMDGPU-NEXT: [[WORKER_WORK_FN:%.*]] = load i8*, i8** [[WORKER_WORK_FN_ADDR_GENERIC]], align 8
1691 ; AMDGPU-NEXT: [[WORKER_WORK_FN_ADDR_CAST:%.*]] = bitcast i8* [[WORKER_WORK_FN]] to void (i16, i…
1692 ; AMDGPU-NEXT: [[WORKER_IS_DONE:%.*]] = icmp eq i8* [[WORKER_WORK_FN]], null
1693 ; AMDGPU-NEXT: br i1 [[WORKER_IS_DONE]], label [[WORKER_STATE_MACHINE_FINISHED]], label [[WORKER…
1694 ; AMDGPU: worker_state_machine.finished:
1695 ; AMDGPU-NEXT: ret void
1696 ; AMDGPU: worker_state_machine.is_active.check:
1697 ; AMDGPU-NEXT: br i1 [[WORKER_IS_ACTIVE]], label [[WORKER_STATE_MACHINE_PARALLEL_REGION_FALLBACK…
1698 ; AMDGPU: worker_state_machine.parallel_region.fallback.execute:
1699 ; AMDGPU-NEXT: call void [[WORKER_WORK_FN_ADDR_CAST]](i16 0, i32 [[TMP0]])
1700 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_PARALLEL_REGION_END:%.*]]
1701 ; AMDGPU: worker_state_machine.parallel_region.end:
1702 ; AMDGPU-NEXT: call void @__kmpc_kernel_end_parallel()
1703 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_DONE_BARRIER]]
1704 ; AMDGPU: worker_state_machine.done.barrier:
1705 ; AMDGPU-NEXT: call void @__kmpc_barrier_simple_generic(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]…
1706 ; AMDGPU-NEXT: br label [[WORKER_STATE_MACHINE_BEGIN]]
1707 ; AMDGPU: thread.user_code.check:
1708 ; AMDGPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
1709 ; AMDGPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1710 ; AMDGPU: user_code.entry:
1711 ; AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) #[…
1712 ; AMDGPU-NEXT: call void @__omp_outlined__16(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) …
1713 ; AMDGPU-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
1714 ; AMDGPU-NEXT: ret void
1715 ; AMDGPU: worker.exit:
1716 ; AMDGPU-NEXT: ret void
1719 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1720 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__16
1721 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1722 ; AMDGPU-NEXT: entry:
1723 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1724 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1725 ; AMDGPU-NEXT: call void @weak_callee_empty() #[[ATTR8]]
1726 ; AMDGPU-NEXT: ret void
1729 ; AMDGPU: Function Attrs: convergent noinline nounwind
1730 ; AMDGPU-LABEL: define {{[^@]+}}@weak_callee_empty
1731 ; AMDGPU-SAME: () #[[ATTR1]] {
1732 ; AMDGPU-NEXT: entry:
1733 ; AMDGPU-NEXT: ret void
1736 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1737 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17
1738 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1739 ; AMDGPU-NEXT: entry:
1740 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1741 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1742 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1743 ; AMDGPU-NEXT: ret void
1746 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1747 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
1748 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1749 ; AMDGPU-NEXT: entry:
1750 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1751 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1752 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1753 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1754 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1755 ; AMDGPU-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1756 ; AMDGPU-NEXT: ret void
1759 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1760 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18
1761 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1762 ; AMDGPU-NEXT: entry:
1763 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1764 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1765 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1766 ; AMDGPU-NEXT: ret void
1769 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1770 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
1771 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1772 ; AMDGPU-NEXT: entry:
1773 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1774 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1775 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1776 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1777 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1778 ; AMDGPU-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1779 ; AMDGPU-NEXT: ret void
1782 ; AMDGPU: Function Attrs: convergent noinline nounwind
1783 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.…
1784 ; AMDGPU-SAME: () #[[ATTR1]] {
1785 ; AMDGPU-NEXT: entry:
1786 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1787 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) #[…
1788 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1789 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1790 ; AMDGPU-NEXT: ret void
1793 ; AMDGPU: Function Attrs: convergent noinline nounwind
1794 ; AMDGPU-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
1795 ; AMDGPU-SAME: () #[[ATTR1]] {
1796 ; AMDGPU-NEXT: entry:
1797 ; AMDGPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
1798 ; AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
1799 ; AMDGPU-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
1800 ; AMDGPU-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i…
1801 ; AMDGPU-NEXT: ret void
1804 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1805 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19
1806 ; AMDGPU-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]]…
1807 ; AMDGPU-NEXT: entry:
1808 ; AMDGPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1809 ; AMDGPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1810 ; AMDGPU-NEXT: call void @p0() #[[ATTR10]]
1811 ; AMDGPU-NEXT: ret void
1814 ; AMDGPU: Function Attrs: convergent noinline norecurse nounwind
1815 ; AMDGPU-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
1816 ; AMDGPU-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
1817 ; AMDGPU-NEXT: entry:
1818 ; AMDGPU-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
1819 ; AMDGPU-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
1820 ; AMDGPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1821 ; AMDGPU-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
1822 ; AMDGPU-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
1823 ; AMDGPU-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
1824 ; AMDGPU-NEXT: ret void
2803 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2804 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
2805 ; AMDGPU-DISABLED-SAME: () #[[ATTR0:[0-9]+]] {
2806 ; AMDGPU-DISABLED-NEXT: entry:
2807 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2808 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2809 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0…
2810 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2811 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2812 ; AMDGPU-DISABLED: user_code.entry:
2813 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2814 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_A…
2815 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2816 ; AMDGPU-DISABLED-NEXT: ret void
2817 ; AMDGPU-DISABLED: worker.exit:
2818 ; AMDGPU-DISABLED-NEXT: ret void
2821 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2822 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__
2823 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2824 ; AMDGPU-DISABLED-NEXT: entry:
2825 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2826 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2827 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8:[0-9]+]]
2828 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9:[0-9]+]]
2829 ; AMDGPU-DISABLED-NEXT: ret void
2832 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2833 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
2834 ; AMDGPU-DISABLED-SAME: () #[[ATTR1:[0-9]+]] {
2835 ; AMDGPU-DISABLED-NEXT: entry:
2836 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2837 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 …
2838 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2839 ; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2840 ; AMDGPU-DISABLED: omp_if.then:
2841 ; AMDGPU-DISABLED-NEXT: store i32 0, i32* @G, align 4
2842 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) …
2843 ; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
2844 ; AMDGPU-DISABLED: omp_if.end:
2845 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0…
2846 ; AMDGPU-DISABLED-NEXT: ret void
2849 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2850 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@no_parallel_region_in_here
2851 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
2852 ; AMDGPU-DISABLED-NEXT: entry:
2853 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2854 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(%struct.ident_t* @[[GLOB2]], i32 …
2855 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
2856 ; AMDGPU-DISABLED-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
2857 ; AMDGPU-DISABLED: omp_if.then:
2858 ; AMDGPU-DISABLED-NEXT: store i32 0, i32* @G, align 4
2859 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_end_single(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]])
2860 ; AMDGPU-DISABLED-NEXT: br label [[OMP_IF_END]]
2861 ; AMDGPU-DISABLED: omp_if.end:
2862 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
2863 ; AMDGPU-DISABLED-NEXT: ret void
2866 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2867 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
2868 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
2869 ; AMDGPU-DISABLED-NEXT: entry:
2870 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2871 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2872 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
2873 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2874 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2875 ; AMDGPU-DISABLED: user_code.entry:
2876 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2877 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
2878 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
2879 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2880 ; AMDGPU-DISABLED-NEXT: ret void
2881 ; AMDGPU-DISABLED: worker.exit:
2882 ; AMDGPU-DISABLED-NEXT: ret void
2885 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2886 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__1
2887 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2888 ; AMDGPU-DISABLED-NEXT: entry:
2889 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2890 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2891 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2892 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
2893 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2894 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
2895 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2896 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2897 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2898 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2899 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
2900 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
2901 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2902 ; AMDGPU-DISABLED-NEXT: ret void
2905 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2906 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2
2907 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2908 ; AMDGPU-DISABLED-NEXT: entry:
2909 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2910 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2911 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10:[0-9]+]]
2912 ; AMDGPU-DISABLED-NEXT: ret void
2915 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2916 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
2917 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
2918 ; AMDGPU-DISABLED-NEXT: entry:
2919 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
2920 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
2921 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2922 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
2923 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
2924 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__2(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
2925 ; AMDGPU-DISABLED-NEXT: ret void
2928 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2929 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3
2930 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2931 ; AMDGPU-DISABLED-NEXT: entry:
2932 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2933 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2934 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
2935 ; AMDGPU-DISABLED-NEXT: ret void
2938 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2939 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
2940 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
2941 ; AMDGPU-DISABLED-NEXT: entry:
2942 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
2943 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
2944 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2945 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
2946 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
2947 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__3(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
2948 ; AMDGPU-DISABLED-NEXT: ret void
2951 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2952 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interpro…
2953 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
2954 ; AMDGPU-DISABLED-NEXT: entry:
2955 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2956 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2957 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
2958 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
2959 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
2960 ; AMDGPU-DISABLED: user_code.entry:
2961 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2962 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
2963 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
2964 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
2965 ; AMDGPU-DISABLED-NEXT: ret void
2966 ; AMDGPU-DISABLED: worker.exit:
2967 ; AMDGPU-DISABLED-NEXT: ret void
2970 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
2971 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__4
2972 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
2973 ; AMDGPU-DISABLED-NEXT: entry:
2974 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2975 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2976 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2977 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2978 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
2979 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_before.internalized() #[…
2980 ; AMDGPU-DISABLED-NEXT: call void @no_parallel_region_in_here.internalized() #[[ATTR8]]
2981 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2982 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
2983 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2984 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
2985 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_after.internalized() #[[…
2986 ; AMDGPU-DISABLED-NEXT: ret void
2989 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
2990 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
2991 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
2992 ; AMDGPU-DISABLED-NEXT: entry:
2993 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
2994 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
2995 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
2996 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
2997 ; AMDGPU-DISABLED-NEXT: ret void
3000 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3001 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
3002 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3003 ; AMDGPU-DISABLED-NEXT: entry:
3004 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3005 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3006 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3007 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3008 ; AMDGPU-DISABLED-NEXT: ret void
3011 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3012 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5
3013 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3014 ; AMDGPU-DISABLED-NEXT: entry:
3015 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3016 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3017 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3018 ; AMDGPU-DISABLED-NEXT: ret void
3021 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3022 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
3023 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3024 ; AMDGPU-DISABLED-NEXT: entry:
3025 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3026 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3027 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3028 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3029 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3030 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__5(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3031 ; AMDGPU-DISABLED-NEXT: ret void
3034 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3035 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
3036 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3037 ; AMDGPU-DISABLED-NEXT: entry:
3038 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3039 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3040 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3041 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3042 ; AMDGPU-DISABLED-NEXT: ret void
3045 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3046 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
3047 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3048 ; AMDGPU-DISABLED-NEXT: entry:
3049 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3050 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3051 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3052 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3053 ; AMDGPU-DISABLED-NEXT: ret void
3056 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3057 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fal…
3058 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3059 ; AMDGPU-DISABLED-NEXT: entry:
3060 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3061 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3062 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3063 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3064 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3065 ; AMDGPU-DISABLED: user_code.entry:
3066 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3067 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3068 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
3069 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3070 ; AMDGPU-DISABLED-NEXT: ret void
3071 ; AMDGPU-DISABLED: worker.exit:
3072 ; AMDGPU-DISABLED-NEXT: ret void
3075 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3076 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__6
3077 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3078 ; AMDGPU-DISABLED-NEXT: entry:
3079 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3080 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3081 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3082 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3083 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3084 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3085 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3086 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3087 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3088 ; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 @unknown() #[[ATTR10]]
3089 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3090 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3091 ; AMDGPU-DISABLED-NEXT: ret void
3094 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3095 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7
3096 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3097 ; AMDGPU-DISABLED-NEXT: entry:
3098 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3099 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3100 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3101 ; AMDGPU-DISABLED-NEXT: ret void
3104 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3105 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
3106 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3107 ; AMDGPU-DISABLED-NEXT: entry:
3108 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3109 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3110 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3111 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3112 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3113 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__7(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3114 ; AMDGPU-DISABLED-NEXT: ret void
3117 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3118 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8
3119 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3120 ; AMDGPU-DISABLED-NEXT: entry:
3121 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3122 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3123 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3124 ; AMDGPU-DISABLED-NEXT: ret void
3127 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3128 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
3129 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3130 ; AMDGPU-DISABLED-NEXT: entry:
3131 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3132 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3133 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3134 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3135 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3136 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__8(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) #…
3137 ; AMDGPU-DISABLED-NEXT: ret void
3140 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3141 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openm…
3142 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3143 ; AMDGPU-DISABLED-NEXT: entry:
3144 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3145 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3146 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3147 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3148 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3149 ; AMDGPU-DISABLED: user_code.entry:
3150 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3151 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3152 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__9(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_…
3153 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3154 ; AMDGPU-DISABLED-NEXT: ret void
3155 ; AMDGPU-DISABLED: worker.exit:
3156 ; AMDGPU-DISABLED-NEXT: ret void
3159 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3160 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__9
3161 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3162 ; AMDGPU-DISABLED-NEXT: entry:
3163 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3164 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3165 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3166 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3167 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3168 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3169 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3170 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3171 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3172 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3173 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3174 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3175 ; AMDGPU-DISABLED-NEXT: ret void
3178 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3179 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10
3180 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3181 ; AMDGPU-DISABLED-NEXT: entry:
3182 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3183 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3184 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3185 ; AMDGPU-DISABLED-NEXT: ret void
3188 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3189 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
3190 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3191 ; AMDGPU-DISABLED-NEXT: entry:
3192 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3193 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3194 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3195 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3196 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3197 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__10(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3198 ; AMDGPU-DISABLED-NEXT: ret void
3201 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3202 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11
3203 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3204 ; AMDGPU-DISABLED-NEXT: entry:
3205 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3206 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3207 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3208 ; AMDGPU-DISABLED-NEXT: ret void
3211 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3212 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
3213 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3214 ; AMDGPU-DISABLED-NEXT: entry:
3215 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3216 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3217 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3218 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3219 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3220 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__11(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3221 ; AMDGPU-DISABLED-NEXT: ret void
3224 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3225 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
3226 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3227 ; AMDGPU-DISABLED-NEXT: entry:
3228 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3229 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3230 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3231 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3232 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3233 ; AMDGPU-DISABLED: user_code.entry:
3234 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3235 ; AMDGPU-DISABLED-NEXT: store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
3236 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__12(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3237 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3238 ; AMDGPU-DISABLED-NEXT: ret void
3239 ; AMDGPU-DISABLED: worker.exit:
3240 ; AMDGPU-DISABLED-NEXT: ret void
3243 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3244 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__12
3245 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3246 ; AMDGPU-DISABLED-NEXT: entry:
3247 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3248 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3249 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3250 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x i8*], align 8
3251 ; AMDGPU-DISABLED-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3252 ; AMDGPU-DISABLED-NEXT: call void @unknown_no_openmp() #[[ATTR9]]
3253 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3254 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3255 ; AMDGPU-DISABLED-NEXT: [[TMP2:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3256 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3257 ; AMDGPU-DISABLED-NEXT: [[TMP3:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS1]] to i8**
3258 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]],…
3259 ; AMDGPU-DISABLED-NEXT: ret void
3262 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3263 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13
3264 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3265 ; AMDGPU-DISABLED-NEXT: entry:
3266 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3267 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3268 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3269 ; AMDGPU-DISABLED-NEXT: ret void
3272 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3273 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
3274 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3275 ; AMDGPU-DISABLED-NEXT: entry:
3276 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3277 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3278 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3279 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3280 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3281 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__13(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3282 ; AMDGPU-DISABLED-NEXT: ret void
3285 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3286 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14
3287 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3288 ; AMDGPU-DISABLED-NEXT: entry:
3289 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3290 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3291 ; AMDGPU-DISABLED-NEXT: call void @p1() #[[ATTR10]]
3292 ; AMDGPU-DISABLED-NEXT: ret void
3295 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3296 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
3297 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3298 ; AMDGPU-DISABLED-NEXT: entry:
3299 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3300 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3301 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3302 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3303 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3304 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__14(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3305 ; AMDGPU-DISABLED-NEXT: ret void
3308 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3309 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interpro…
3310 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3311 ; AMDGPU-DISABLED-NEXT: entry:
3312 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3313 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3314 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3315 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3316 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3317 ; AMDGPU-DISABLED: user_code.entry:
3318 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3319 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__15(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3320 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3321 ; AMDGPU-DISABLED-NEXT: ret void
3322 ; AMDGPU-DISABLED: worker.exit:
3323 ; AMDGPU-DISABLED-NEXT: ret void
3326 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3327 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__15
3328 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3329 ; AMDGPU-DISABLED-NEXT: entry:
3330 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3331 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3332 ; AMDGPU-DISABLED-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @omp_get_thread_num to i32 (…
3333 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.i…
3334 ; AMDGPU-DISABLED-NEXT: ret void
3337 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3338 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3339 ; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
3340 ; AMDGPU-DISABLED-NEXT: entry:
3341 ; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3342 ; AMDGPU-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3343 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3344 ; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
3345 ; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
3346 ; AMDGPU-DISABLED: if.then:
3347 ; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
3348 ; AMDGPU-DISABLED: if.end:
3349 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3350 ; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
3351 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after.i…
3352 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_a…
3353 ; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
3354 ; AMDGPU-DISABLED: return:
3355 ; AMDGPU-DISABLED-NEXT: ret void
3358 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3359 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3360 ; AMDGPU-DISABLED-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
3361 ; AMDGPU-DISABLED-NEXT: entry:
3362 ; AMDGPU-DISABLED-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3363 ; AMDGPU-DISABLED-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3364 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3365 ; AMDGPU-DISABLED-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
3366 ; AMDGPU-DISABLED-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
3367 ; AMDGPU-DISABLED: if.then:
3368 ; AMDGPU-DISABLED-NEXT: br label [[RETURN:%.*]]
3369 ; AMDGPU-DISABLED: if.end:
3370 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3371 ; AMDGPU-DISABLED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
3372 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after(i…
3373 ; AMDGPU-DISABLED-NEXT: call void @simple_state_machine_interprocedural_nested_recursive_after_a…
3374 ; AMDGPU-DISABLED-NEXT: br label [[RETURN]]
3375 ; AMDGPU-DISABLED: return:
3376 ; AMDGPU-DISABLED-NEXT: ret void
3379 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3380 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_…
3381 ; AMDGPU-DISABLED-SAME: () #[[ATTR0]] {
3382 ; AMDGPU-DISABLED-NEXT: entry:
3383 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3384 ; AMDGPU-DISABLED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3385 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1]],…
3386 ; AMDGPU-DISABLED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
3387 ; AMDGPU-DISABLED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_…
3388 ; AMDGPU-DISABLED: user_code.entry:
3389 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3390 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__16(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO…
3391 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 tr…
3392 ; AMDGPU-DISABLED-NEXT: ret void
3393 ; AMDGPU-DISABLED: worker.exit:
3394 ; AMDGPU-DISABLED-NEXT: ret void
3397 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3398 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__16
3399 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3400 ; AMDGPU-DISABLED-NEXT: entry:
3401 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3402 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3403 ; AMDGPU-DISABLED-NEXT: call void @weak_callee_empty() #[[ATTR8]]
3404 ; AMDGPU-DISABLED-NEXT: ret void
3407 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3408 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@weak_callee_empty
3409 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3410 ; AMDGPU-DISABLED-NEXT: entry:
3411 ; AMDGPU-DISABLED-NEXT: ret void
3414 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3415 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17
3416 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3417 ; AMDGPU-DISABLED-NEXT: entry:
3418 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3419 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3420 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3421 ; AMDGPU-DISABLED-NEXT: ret void
3424 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3425 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
3426 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3427 ; AMDGPU-DISABLED-NEXT: entry:
3428 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3429 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3430 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3431 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3432 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3433 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__17(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3434 ; AMDGPU-DISABLED-NEXT: ret void
3437 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3438 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18
3439 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3440 ; AMDGPU-DISABLED-NEXT: entry:
3441 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3442 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3443 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3444 ; AMDGPU-DISABLED-NEXT: ret void
3447 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3448 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
3449 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3450 ; AMDGPU-DISABLED-NEXT: entry:
3451 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3452 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3453 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3454 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3455 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3456 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__18(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3457 ; AMDGPU-DISABLED-NEXT: ret void
3460 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3461 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3462 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3463 ; AMDGPU-DISABLED-NEXT: entry:
3464 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3465 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3466 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3467 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3468 ; AMDGPU-DISABLED-NEXT: ret void
3471 ; AMDGPU-DISABLED: Function Attrs: convergent noinline nounwind
3472 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_aft…
3473 ; AMDGPU-DISABLED-SAME: () #[[ATTR1]] {
3474 ; AMDGPU-DISABLED-NEXT: entry:
3475 ; AMDGPU-DISABLED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x i8*], align 8
3476 ; AMDGPU-DISABLED-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GL…
3477 ; AMDGPU-DISABLED-NEXT: [[TMP1:%.*]] = bitcast [0 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
3478 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]],…
3479 ; AMDGPU-DISABLED-NEXT: ret void
3482 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3483 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19
3484 ; AMDGPU-DISABLED-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #…
3485 ; AMDGPU-DISABLED-NEXT: entry:
3486 ; AMDGPU-DISABLED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3487 ; AMDGPU-DISABLED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3488 ; AMDGPU-DISABLED-NEXT: call void @p0() #[[ATTR10]]
3489 ; AMDGPU-DISABLED-NEXT: ret void
3492 ; AMDGPU-DISABLED: Function Attrs: convergent noinline norecurse nounwind
3493 ; AMDGPU-DISABLED-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
3494 ; AMDGPU-DISABLED-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
3495 ; AMDGPU-DISABLED-NEXT: entry:
3496 ; AMDGPU-DISABLED-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
3497 ; AMDGPU-DISABLED-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
3498 ; AMDGPU-DISABLED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3499 ; AMDGPU-DISABLED-NEXT: [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
3500 ; AMDGPU-DISABLED-NEXT: call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
3501 ; AMDGPU-DISABLED-NEXT: call void @__omp_outlined__19(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]]) …
3502 ; AMDGPU-DISABLED-NEXT: ret void