142       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit16Encoding()
178       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit32Encoding()
214       STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])  in getLit64Encoding()
241   case AMDGPU::OPERAND_REG_IMM_INT32:  in getLitEncoding()
242   case AMDGPU::OPERAND_REG_IMM_FP32:  in getLitEncoding()
243   case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:  in getLitEncoding()
244   case AMDGPU::OPERAND_REG_INLINE_C_INT32:  in getLitEncoding()
245   case AMDGPU::OPERAND_REG_INLINE_C_FP32:  in getLitEncoding()
246   case AMDGPU::OPERAND_REG_INLINE_AC_INT32:  in getLitEncoding()
247   case AMDGPU::OPERAND_REG_INLINE_AC_FP32:  in getLitEncoding()
248   case AMDGPU::OPERAND_REG_IMM_V2INT32:  in getLitEncoding()
249   case AMDGPU::OPERAND_REG_IMM_V2FP32:  in getLitEncoding()
250   case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:  in getLitEncoding()
251   case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:  in getLitEncoding()
254   case AMDGPU::OPERAND_REG_IMM_INT64:  in getLitEncoding()
255   case AMDGPU::OPERAND_REG_IMM_FP64:  in getLitEncoding()
256   case AMDGPU::OPERAND_REG_INLINE_C_INT64:  in getLitEncoding()
257   case AMDGPU::OPERAND_REG_INLINE_C_FP64:  in getLitEncoding()
258   case AMDGPU::OPERAND_REG_INLINE_AC_FP64:  in getLitEncoding()
261   case AMDGPU::OPERAND_REG_IMM_INT16:  in getLitEncoding()
262   case AMDGPU::OPERAND_REG_INLINE_C_INT16:  in getLitEncoding()
263   case AMDGPU::OPERAND_REG_INLINE_AC_INT16:  in getLitEncoding()
265   case AMDGPU::OPERAND_REG_IMM_FP16:  in getLitEncoding()
266   case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:  in getLitEncoding()
267   case AMDGPU::OPERAND_REG_INLINE_C_FP16:  in getLitEncoding()
268   case AMDGPU::OPERAND_REG_INLINE_AC_FP16:  in getLitEncoding()
272   case AMDGPU::OPERAND_REG_IMM_V2INT16:  in getLitEncoding()
273   case AMDGPU::OPERAND_REG_IMM_V2FP16: {  in getLitEncoding()
274     if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])  in getLitEncoding()
276     if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)  in getLitEncoding()
280   case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:  in getLitEncoding()
281   case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:  in getLitEncoding()
283   case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:  in getLitEncoding()
284   case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {  in getLitEncoding()
289   case AMDGPU::OPERAND_KIMM32:  in getLitEncoding()
290   case AMDGPU::OPERAND_KIMM16:  in getLitEncoding()
298   using namespace AMDGPU::VOP3PEncoding;  in getImplicitOpSelHiEncoding()
299   using namespace AMDGPU::OpName;  in getImplicitOpSelHiEncoding()
301   if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) {  in getImplicitOpSelHiEncoding()
302     if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1)  in getImplicitOpSelHiEncoding()
304     if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1)  in getImplicitOpSelHiEncoding()
306     if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1)  in getImplicitOpSelHiEncoding()
314          Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);  in isVCMPX64()
329       Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||  in encodeInstruction()
330       Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {  in encodeInstruction()
340   if (AMDGPU::isGFX11Plus(STI) && isVCMPX64(Desc)) {  in encodeInstruction()
342     Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO);  in encodeInstruction()
350   if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {  in encodeInstruction()
351     int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
352                                             AMDGPU::OpName::vaddr0);  in encodeInstruction()
353     int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),  in encodeInstruction()
354                                            AMDGPU::OpName::srsrc);  in encodeInstruction()
368   if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||  in encodeInstruction()
369       (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))  in encodeInstruction()
374       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);  in encodeInstruction()
382     if (!AMDGPU::isSISrcOperand(Desc, i))  in encodeInstruction()
419     MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;  in getSOPPBrEncoding()
433   assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));  in getSMEMOffsetEncoding()
441   using namespace AMDGPU::SDWA;  in getSDWASrcEncoding()
451     if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {  in getSDWASrcEncoding()
472   using namespace AMDGPU::SDWA;  in getSDWAVopcDstEncoding()
479   if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {  in getSDWAVopcDstEncoding()
497   if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||  in getAVOperandEncoding()
498       MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||  in getAVOperandEncoding()
499       MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||  in getAVOperandEncoding()
500       MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||  in getAVOperandEncoding()
501       MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||  in getAVOperandEncoding()
502       MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||  in getAVOperandEncoding()
503       MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||  in getAVOperandEncoding()
504       MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||  in getAVOperandEncoding()
505       MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||  in getAVOperandEncoding()
506       MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))  in getAVOperandEncoding()
576   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {  in getMachineOpValueCommon()