Lines Matching refs:AMDGPU
25 using namespace llvm::AMDGPU;
147 if (AMDGPU::isGFX10(STI)) { in printFlatOffset()
208 O << ((AMDGPU::isGFX940(STI) && in printCPol()
212 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
213 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
215 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
216 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
243 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
262 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
303 using namespace llvm::AMDGPU::MTBUFFormat; in printSymbolicFormat()
306 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
310 if (AMDGPU::isGFX10Plus(STI)) { in printSymbolicFormat()
346 case AMDGPU::FP_REG: in printRegOperand()
347 case AMDGPU::SP_REG: in printRegOperand()
348 case AMDGPU::PRIVATE_RSRC_REG: in printRegOperand()
350 case AMDGPU::SCC: in printRegOperand()
391 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printVOPDst()
392 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printVOPDst()
393 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printVOPDst()
394 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printVOPDst()
395 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printVOPDst()
396 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printVOPDst()
397 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printVOPDst()
398 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printVOPDst()
399 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printVOPDst()
400 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printVOPDst()
401 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printVOPDst()
402 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printVOPDst()
403 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printVOPDst()
404 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printVOPDst()
405 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printVOPDst()
406 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printVOPDst()
407 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printVOPDst()
408 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printVOPDst()
409 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printVOPDst()
410 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printVOPDst()
411 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printVOPDst()
419 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI)) in printVINTRPDst()
465 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) { in printImmediate16()
508 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate32()
542 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in printImmediate64()
560 if (AMDGPU::isGFX940(STI)) { in printBLGP()
562 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd: in printBLGP()
563 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd: in printBLGP()
564 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd: in printBLGP()
565 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd: in printBLGP()
600 printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] in printDefaultVccOperand()
601 ? AMDGPU::VCC in printDefaultVccOperand()
602 : AMDGPU::VCC_LO, in printDefaultVccOperand()
632 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in needsImpliedVcc()
633 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)); in needsImpliedVcc()
642 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOperand()
649 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) || in printOperand()
650 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO))) in printOperand()
673 case AMDGPU::OPERAND_REG_IMM_INT32: in printRegularOperand()
674 case AMDGPU::OPERAND_REG_IMM_FP32: in printRegularOperand()
675 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in printRegularOperand()
676 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in printRegularOperand()
677 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in printRegularOperand()
678 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in printRegularOperand()
679 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in printRegularOperand()
680 case AMDGPU::OPERAND_REG_IMM_V2INT32: in printRegularOperand()
681 case AMDGPU::OPERAND_REG_IMM_V2FP32: in printRegularOperand()
682 case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: in printRegularOperand()
683 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in printRegularOperand()
687 case AMDGPU::OPERAND_REG_IMM_INT64: in printRegularOperand()
688 case AMDGPU::OPERAND_REG_IMM_FP64: in printRegularOperand()
689 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in printRegularOperand()
690 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in printRegularOperand()
691 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in printRegularOperand()
694 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in printRegularOperand()
695 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in printRegularOperand()
696 case AMDGPU::OPERAND_REG_IMM_INT16: in printRegularOperand()
699 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in printRegularOperand()
700 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in printRegularOperand()
701 case AMDGPU::OPERAND_REG_IMM_FP16: in printRegularOperand()
702 case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: in printRegularOperand()
705 case AMDGPU::OPERAND_REG_IMM_V2INT16: in printRegularOperand()
706 case AMDGPU::OPERAND_REG_IMM_V2FP16: in printRegularOperand()
708 STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in printRegularOperand()
714 if (OpTy == AMDGPU::OPERAND_REG_IMM_V2FP16) { in printRegularOperand()
719 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in printRegularOperand()
720 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in printRegularOperand()
723 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in printRegularOperand()
724 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in printRegularOperand()
749 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
768 case AMDGPU::V_CNDMASK_B32_e32_gfx10: in printRegularOperand()
769 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: in printRegularOperand()
770 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: in printRegularOperand()
771 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in printRegularOperand()
772 case AMDGPU::V_CNDMASK_B32_dpp_gfx10: in printRegularOperand()
773 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: in printRegularOperand()
774 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: in printRegularOperand()
775 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: in printRegularOperand()
776 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10: in printRegularOperand()
777 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
778 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
779 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: in printRegularOperand()
780 case AMDGPU::V_CNDMASK_B32_e32_gfx11: in printRegularOperand()
781 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11: in printRegularOperand()
782 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11: in printRegularOperand()
783 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11: in printRegularOperand()
784 case AMDGPU::V_CNDMASK_B32_dpp_gfx11: in printRegularOperand()
785 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11: in printRegularOperand()
786 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11: in printRegularOperand()
787 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11: in printRegularOperand()
788 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11: in printRegularOperand()
789 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
790 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
791 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11: in printRegularOperand()
793 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: in printRegularOperand()
794 case AMDGPU::V_CNDMASK_B32_e32_vi: in printRegularOperand()
795 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printRegularOperand()
796 AMDGPU::OpName::src1)) in printRegularOperand()
803 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printRegularOperand()
868 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10: in printOperandAndIntInputMods()
869 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
870 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
871 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: in printOperandAndIntInputMods()
872 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printOperandAndIntInputMods()
873 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
882 if (!AMDGPU::isGFX10Plus(STI)) in printDPP8()
896 using namespace AMDGPU::DPP; in printDPPCtrl()
900 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in printDPPCtrl()
901 AMDGPU::OpName::src0); in printDPPCtrl()
904 Desc.OpInfo[Src0Idx].RegClass == AMDGPU::VReg_64RegClassID && in printDPPCtrl()
905 !AMDGPU::isLegal64BitDPPControl(Imm)) { in printDPPCtrl()
927 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
933 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
939 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
945 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
955 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
961 if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
968 if (AMDGPU::isGFX90A(STI)) { in printDPPCtrl()
970 } else if (AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
980 if (!AMDGPU::isGFX10Plus(STI)) { in printDPPCtrl()
1017 using namespace llvm::AMDGPU::DPP; in printFI()
1026 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
1065 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
1081 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1084 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1123 using namespace llvm::AMDGPU::Exp; in printExpTgt()
1162 for (int OpName : { AMDGPU::OpName::src0_modifiers, in printPackedModifier()
1163 AMDGPU::OpName::src1_modifiers, in printPackedModifier()
1164 AMDGPU::OpName::src2_modifiers }) { in printPackedModifier()
1165 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName); in printPackedModifier()
1202 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || in printOpSel()
1203 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { in printOpSel()
1204 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOpSel()
1205 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers); in printOpSel()
1270 using namespace llvm::AMDGPU::VGPRIndexMode; in printVGPRIndexMode()
1345 using namespace llvm::AMDGPU::SendMsg; in printSendMsg()
1377 using namespace llvm::AMDGPU::Swizzle; in printSwizzleBitmask()
1409 using namespace llvm::AMDGPU::Swizzle; in printSwizzle()
1482 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(STI.getCPU()); in printWaitFlag()
1517 using namespace llvm::AMDGPU::DepCtr; in printDepCtr()
1590 using namespace llvm::AMDGPU::Hwreg; in printHwreg()