Lines Matching refs:AMDGPU
118 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT || in applyBank()
119 Opc == AMDGPU::G_SEXT) { in applyBank()
126 if (SrcBank == &AMDGPU::VCCRegBank) { in applyBank()
130 assert(NewBank == &AMDGPU::VGPRRegBank); in applyBank()
135 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
149 if (Opc == AMDGPU::G_TRUNC) { in applyBank()
152 assert(DstBank != &AMDGPU::VCCRegBank); in applyBank()
167 assert(NewBank == &AMDGPU::VGPRRegBank && in applyBank()
169 assert((MI.getOpcode() != AMDGPU::G_TRUNC && in applyBank()
170 MI.getOpcode() != AMDGPU::G_ANYEXT) && in applyBank()
172 RB = &AMDGPU::VCCRegBank; in applyBank()
204 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && in AMDGPURegisterBankInfo()
205 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && in AMDGPURegisterBankInfo()
206 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); in AMDGPURegisterBankInfo()
215 return BankID == AMDGPU::VGPRRegBankID || BankID == AMDGPU::AGPRRegBankID; in isVectorRegisterBank()
222 if (Dst.getID() == AMDGPU::SGPRRegBankID && in copyCost()
223 (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) { in copyCost()
235 (Dst.getID() == AMDGPU::SGPRRegBankID) && in copyCost()
237 Src.getID() == AMDGPU::SGPRRegBankID || in copyCost()
238 Src.getID() == AMDGPU::VCCRegBankID)) in copyCost()
242 if (Dst.getID() == AMDGPU::AGPRRegBankID && in copyCost()
243 Src.getID() == AMDGPU::AGPRRegBankID) in copyCost()
277 if (&RC == &AMDGPU::SReg_1RegClass) in getRegBankFromRegClass()
278 return AMDGPU::VCCRegBank; in getRegBankFromRegClass()
287 return AMDGPU::SGPRRegBank; in getRegBankFromRegClass()
289 return Ty == LLT::scalar(1) ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank; in getRegBankFromRegClass()
292 return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank; in getRegBankFromRegClass()
314 Operands[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SizeI); in addMappingFromTable()
322 Operands[OpIdx] = AMDGPU::getValueMapping(Entry.RegBanks[I], Sizes[I]); in addMappingFromTable()
340 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsic()
343 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsic()
352 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
355 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
358 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
361 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
381 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
384 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 300 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
387 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1000 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
390 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1500 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
402 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
405 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
416 { { AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
419 { { AMDGPU::VGPRRegBankID }, 3 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
466 { { AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
467 { { AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
468 { { AMDGPU::VCCRegBankID }, 1 } in getInstrAlternativeMappings()
480 { { AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
481 { { AMDGPU::SGPRRegBankID }, 1 } in getInstrAlternativeMappings()
495 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32), in getInstrAlternativeMappings()
496 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32), in getInstrAlternativeMappings()
497 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32)}), in getInstrAlternativeMappings()
503 {AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size), in getInstrAlternativeMappings()
504 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size), in getInstrAlternativeMappings()
505 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size)}), in getInstrAlternativeMappings()
516 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
517 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
518 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}), in getInstrAlternativeMappings()
524 {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
525 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
526 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}), in getInstrAlternativeMappings()
544 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
545 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize)}), in getInstrAlternativeMappings()
553 {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
554 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize)}), in getInstrAlternativeMappings()
570 getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
571 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), in getInstrAlternativeMappings()
572 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
573 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}), in getInstrAlternativeMappings()
578 getOperandsMapping({AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
579 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), in getInstrAlternativeMappings()
580 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
581 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}), in getInstrAlternativeMappings()
594 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
595 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), in getInstrAlternativeMappings()
596 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
597 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
598 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}), in getInstrAlternativeMappings()
603 getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
604 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), in getInstrAlternativeMappings()
605 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
606 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
607 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1)}), in getInstrAlternativeMappings()
612 case AMDGPU::G_BRCOND: { in getInstrAlternativeMappings()
618 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), nullptr}), in getInstrAlternativeMappings()
624 {AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), nullptr }), in getInstrAlternativeMappings()
629 case AMDGPU::G_INTRINSIC: in getInstrAlternativeMappings()
631 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: in getInstrAlternativeMappings()
655 B.buildInstr(AMDGPU::G_UNMERGE_VALUES) in split64BitValueForMapping()
689 if (Bank == &AMDGPU::SGPRRegBank) in buildReadFirstLane()
695 if (Bank != &AMDGPU::VGPRRegBank) { in buildReadFirstLane()
698 MRI.setRegBank(Src, AMDGPU::VGPRRegBank); in buildReadFirstLane()
716 Register DstPart = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in buildReadFirstLane()
720 constrainGenericRegister(SrcPart, AMDGPU::VGPR_32RegClass, MRI); in buildReadFirstLane()
724 B.buildInstr(AMDGPU::V_READFIRSTLANE_B32, {DstPart}, {SrcPart}); in buildReadFirstLane()
733 MRI.setRegBank(Dst, AMDGPU::SGPRRegBank); in buildReadFirstLane()
770 Subtarget.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in executeInWaterfallLoop()
772 Subtarget.isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
775 AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term; in executeInWaterfallLoop()
777 AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in executeInWaterfallLoop()
779 AMDGPU::EXEC_LO : AMDGPU::EXEC; in executeInWaterfallLoop()
868 if (OpBank != &AMDGPU::VGPRRegBank) { in executeInWaterfallLoop()
872 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
896 MRI.setRegBank(OpParts[i], AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
897 MRI.setRegBank(CurrentLaneParts[i], AMDGPU::SGPRRegBank); in executeInWaterfallLoop()
904 MRI.setRegBank(CmpReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
910 MRI.setRegBank(CondReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
948 B.buildInstr(AMDGPU::SI_WATERFALL_LOOP).addMBB(LoopBB); in executeInWaterfallLoop()
978 if (OpBank->getID() != AMDGPU::SGPRRegBankID) in collectWaterfallOperands()
1013 if (Bank == &AMDGPU::SGPRRegBank) in constrainOpWithReadfirstlane()
1059 if (DstBank == &AMDGPU::SGPRRegBank) { in applyMappingLoad()
1077 ApplyRegBankMapping O(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingLoad()
1084 if (MI.getOpcode() == AMDGPU::G_SEXTLOAD) { in applyMappingLoad()
1088 } else if (MI.getOpcode() == AMDGPU::G_ZEXTLOAD) { in applyMappingLoad()
1145 ApplyRegBankMapping Observer(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingLoad()
1157 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingLoad()
1181 if (SizeBank != &AMDGPU::SGPRRegBank) in applyMappingDynStackAlloc()
1189 ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingDynStackAlloc()
1257 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1263 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1264 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1273 AMDGPU::getBaseWithConstantOffset(*MRI, CombinedOffset); in setBufferOffsets()
1276 if ((int)Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1278 if (RBI.getRegBank(Base, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1281 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1289 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1297 MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI); in setBufferOffsets()
1305 if (Src0Bank == &AMDGPU::VGPRRegBank && Src1Bank == &AMDGPU::SGPRRegBank) { in setBufferOffsets()
1311 if (Src0Bank == &AMDGPU::SGPRRegBank && Src1Bank == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1320 if (RBI.getRegBank(CombinedOffset, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1324 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1328 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1345 if (RSrcBank == &AMDGPU::SGPRRegBank && in applyMappingSBufferLoad()
1346 OffsetBank == &AMDGPU::SGPRRegBank) in applyMappingSBufferLoad()
1390 B.getMRI()->setRegBank(VIndex, AMDGPU::VGPRRegBank); in applyMappingSBufferLoad()
1402 MRI.setRegBank(LoadParts[i], AMDGPU::VGPRRegBank); in applyMappingSBufferLoad()
1409 B.buildInstr(AMDGPU::G_AMDGPU_BUFFER_LOAD) in applyMappingSBufferLoad()
1424 if (RSrcBank != &AMDGPU::SGPRRegBank) { in applyMappingSBufferLoad()
1445 if (RSrcBank == &AMDGPU::SGPRRegBank) in applyMappingSBufferLoad()
1464 unsigned FirstOpnd = MI.getOpcode() == AMDGPU::G_INTRINSIC ? 2 : 1; in applyMappingBFE()
1471 if (DstBank == &AMDGPU::VGPRRegBank) { in applyMappingBFE()
1477 ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingBFE()
1530 ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingBFE()
1547 unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) : in applyMappingBFE()
1548 (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64); in applyMappingBFE()
1572 if (MRI.getRegBankOrNull(Src0) == &AMDGPU::VGPRRegBank) in applyMappingMAD_64_32()
1575 bool IsUnsigned = MI.getOpcode() == AMDGPU::G_AMDGPU_MAD_U64_U32; in applyMappingMAD_64_32()
1579 bool DstOnValu = MRI.getRegBankOrNull(Src2) == &AMDGPU::VGPRRegBank; in applyMappingMAD_64_32()
1594 MRI.setRegBank(DstLo, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1599 MRI.setRegBank(DstHi, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1604 MRI.setRegBank(VSrc0, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1605 MRI.setRegBank(VSrc1, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1609 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1627 DstOnValu ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank; in applyMappingMAD_64_32()
1629 DstOnValu ? AMDGPU::VGPRRegBank : AMDGPU::SGPRRegBank; in applyMappingMAD_64_32()
1636 MulHiInVgpr ? AMDGPU::VGPRRegBank : AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1640 MRI.setRegBank(Carry, MulHiInVgpr ? AMDGPU::VCCRegBank in applyMappingMAD_64_32()
1641 : AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1645 MRI.setRegBank(Carry, AMDGPU::VCCRegBank); in applyMappingMAD_64_32()
1653 MRI.setRegBank(DstLo, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1654 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1851 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1854 return constrainGenericRegister(DstReg, AMDGPU::VGPR_32RegClass, MRI) && in buildVCopy()
1855 constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI); in buildVCopy()
1858 Register TmpReg0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in buildVCopy()
1859 Register TmpReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in buildVCopy()
1861 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1863 .addUse(SrcReg, 0, AMDGPU::sub0); in buildVCopy()
1864 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1866 .addUse(SrcReg, 0, AMDGPU::sub1); in buildVCopy()
1867 B.buildInstr(AMDGPU::REG_SEQUENCE) in buildVCopy()
1870 .addImm(AMDGPU::sub0) in buildVCopy()
1872 .addImm(AMDGPU::sub1); in buildVCopy()
1874 return constrainGenericRegister(SrcReg, AMDGPU::SReg_64RegClass, MRI) && in buildVCopy()
1875 constrainGenericRegister(DstReg, AMDGPU::VReg_64RegClass, MRI); in buildVCopy()
1892 MRI.setRegBank(MaterializedOffset.getReg(0), AMDGPU::SGPRRegBank); in reinsertVectorIndexAdd()
1893 MRI.setRegBank(Add.getReg(0), AMDGPU::SGPRRegBank); in reinsertVectorIndexAdd()
1906 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1908 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1920 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
1935 bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank; in foldExtractEltToCmpSelect()
1954 (DstBank == AMDGPU::SGPRRegBank && in foldExtractEltToCmpSelect()
1955 SrcBank == AMDGPU::SGPRRegBank && in foldExtractEltToCmpSelect()
1956 IdxBank == AMDGPU::SGPRRegBank) ? AMDGPU::SGPRRegBank in foldExtractEltToCmpSelect()
1957 : AMDGPU::VCCRegBank; in foldExtractEltToCmpSelect()
1958 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1); in foldExtractEltToCmpSelect()
1960 if (CCBank == AMDGPU::VCCRegBank && IdxBank == AMDGPU::SGPRRegBank) { in foldExtractEltToCmpSelect()
1962 MRI.setRegBank(Idx, AMDGPU::VGPRRegBank); in foldExtractEltToCmpSelect()
1980 MRI.setRegBank(IC->getOperand(0).getReg(), AMDGPU::SGPRRegBank); in foldExtractEltToCmpSelect()
2033 bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank; in foldInsertEltToCmpSelect()
2054 (DstBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2055 SrcBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2056 InsBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2057 IdxBank == AMDGPU::SGPRRegBank) ? AMDGPU::SGPRRegBank in foldInsertEltToCmpSelect()
2058 : AMDGPU::VCCRegBank; in foldInsertEltToCmpSelect()
2059 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1); in foldInsertEltToCmpSelect()
2061 if (CCBank == AMDGPU::VCCRegBank && IdxBank == AMDGPU::SGPRRegBank) { in foldInsertEltToCmpSelect()
2063 MRI.setRegBank(Idx, AMDGPU::VGPRRegBank); in foldInsertEltToCmpSelect()
2081 MRI.setRegBank(IC->getOperand(0).getReg(), AMDGPU::SGPRRegBank); in foldInsertEltToCmpSelect()
2118 case AMDGPU::G_PHI: { in applyMappingImpl()
2127 if (DstBank == &AMDGPU::VCCRegBank) { in applyMappingImpl()
2140 if (SrcBank != &AMDGPU::VCCRegBank) { in applyMappingImpl()
2145 MRI.setRegBank(Copy.getReg(0), AMDGPU::VCCRegBank); in applyMappingImpl()
2167 case AMDGPU::G_ICMP: in applyMappingImpl()
2168 case AMDGPU::G_UADDO: in applyMappingImpl()
2169 case AMDGPU::G_USUBO: in applyMappingImpl()
2170 case AMDGPU::G_UADDE: in applyMappingImpl()
2171 case AMDGPU::G_SADDE: in applyMappingImpl()
2172 case AMDGPU::G_USUBE: in applyMappingImpl()
2173 case AMDGPU::G_SSUBE: { in applyMappingImpl()
2174 unsigned BoolDstOp = Opc == AMDGPU::G_ICMP ? 0 : 1; in applyMappingImpl()
2179 if (DstBank != &AMDGPU::SGPRRegBank) in applyMappingImpl()
2188 MRI.setRegBank(NewDstReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2194 MRI.setRegBank(NewSrcReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2210 case AMDGPU::G_SELECT: { in applyMappingImpl()
2222 if (CondBank == &AMDGPU::SGPRRegBank) { in applyMappingImpl()
2226 MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2264 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2268 case AMDGPU::G_BRCOND: { in applyMappingImpl()
2274 if (CondBank == &AMDGPU::SGPRRegBank) { in applyMappingImpl()
2278 MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2287 case AMDGPU::G_AND: in applyMappingImpl()
2288 case AMDGPU::G_OR: in applyMappingImpl()
2289 case AMDGPU::G_XOR: { in applyMappingImpl()
2298 if (DstBank == &AMDGPU::VCCRegBank) in applyMappingImpl()
2350 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2354 case AMDGPU::G_ABS: { in applyMappingImpl()
2360 if (SrcBank && SrcBank == &AMDGPU::VGPRRegBank) { in applyMappingImpl()
2362 ApplyRegBankMapping Apply(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2372 case AMDGPU::G_ADD: in applyMappingImpl()
2373 case AMDGPU::G_SUB: in applyMappingImpl()
2374 case AMDGPU::G_MUL: in applyMappingImpl()
2375 case AMDGPU::G_SHL: in applyMappingImpl()
2376 case AMDGPU::G_LSHR: in applyMappingImpl()
2377 case AMDGPU::G_ASHR: in applyMappingImpl()
2378 case AMDGPU::G_SMIN: in applyMappingImpl()
2379 case AMDGPU::G_SMAX: in applyMappingImpl()
2380 case AMDGPU::G_UMIN: in applyMappingImpl()
2381 case AMDGPU::G_UMAX: { in applyMappingImpl()
2392 if (DstBank == &AMDGPU::VGPRRegBank) in applyMappingImpl()
2398 ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingImpl()
2421 if (Opc == AMDGPU::G_SHL || Opc == AMDGPU::G_LSHR || in applyMappingImpl()
2422 Opc == AMDGPU::G_ASHR) { in applyMappingImpl()
2431 case AMDGPU::G_SEXT_INREG: { in applyMappingImpl()
2438 ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2465 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2469 case AMDGPU::G_CTPOP: in applyMappingImpl()
2470 case AMDGPU::G_BITREVERSE: { in applyMappingImpl()
2473 if (DstBank == &AMDGPU::SGPRRegBank) in applyMappingImpl()
2482 ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2492 case AMDGPU::G_AMDGPU_FFBH_U32: in applyMappingImpl()
2493 case AMDGPU::G_AMDGPU_FFBL_B32: in applyMappingImpl()
2494 case AMDGPU::G_CTLZ_ZERO_UNDEF: in applyMappingImpl()
2495 case AMDGPU::G_CTTZ_ZERO_UNDEF: { in applyMappingImpl()
2498 if (DstBank == &AMDGPU::SGPRRegBank) in applyMappingImpl()
2513 ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2516 unsigned NewOpc = Opc == AMDGPU::G_CTLZ_ZERO_UNDEF in applyMappingImpl()
2517 ? (unsigned)AMDGPU::G_AMDGPU_FFBH_U32 in applyMappingImpl()
2518 : Opc == AMDGPU::G_CTTZ_ZERO_UNDEF in applyMappingImpl()
2519 ? (unsigned)AMDGPU::G_AMDGPU_FFBL_B32 in applyMappingImpl()
2521 unsigned Idx = NewOpc == AMDGPU::G_AMDGPU_FFBH_U32; in applyMappingImpl()
2525 Opc == AMDGPU::G_CTLZ_ZERO_UNDEF || Opc == AMDGPU::G_CTTZ_ZERO_UNDEF in applyMappingImpl()
2526 ? AMDGPU::G_ADD in applyMappingImpl()
2527 : AMDGPU::G_UADDSAT; in applyMappingImpl()
2534 case AMDGPU::G_SEXT: in applyMappingImpl()
2535 case AMDGPU::G_ZEXT: in applyMappingImpl()
2536 case AMDGPU::G_ANYEXT: { in applyMappingImpl()
2539 const bool Signed = Opc == AMDGPU::G_SEXT; in applyMappingImpl()
2550 SrcBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2551 SrcBank != &AMDGPU::VCCRegBank && in applyMappingImpl()
2562 } else if (Opc == AMDGPU::G_ZEXT) { in applyMappingImpl()
2580 if (SrcBank == &AMDGPU::VCCRegBank) { in applyMappingImpl()
2583 const RegisterBank *DstBank = &AMDGPU::VGPRRegBank; in applyMappingImpl()
2588 SrcBank->getID() == AMDGPU::SGPRRegBankID; in applyMappingImpl()
2616 case AMDGPU::G_BUILD_VECTOR: in applyMappingImpl()
2617 case AMDGPU::G_BUILD_VECTOR_TRUNC: { in applyMappingImpl()
2629 if (DstBank == &AMDGPU::SGPRRegBank) in applyMappingImpl()
2646 if (Opc == AMDGPU::G_BUILD_VECTOR) { in applyMappingImpl()
2679 case AMDGPU::G_EXTRACT_VECTOR_ELT: { in applyMappingImpl()
2707 AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(2).getReg()); in applyMappingImpl()
2713 bool ShouldMoveIndexIntoLoop = IdxBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2725 const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank && in applyMappingImpl()
2726 SrcBank == &AMDGPU::SGPRRegBank; in applyMappingImpl()
2735 MRI.setRegBank(TmpReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2774 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2775 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2776 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2795 MRI.setRegBank(TmpReg0, AMDGPU::SGPRRegBank); in applyMappingImpl()
2796 MRI.setRegBank(TmpReg1, AMDGPU::SGPRRegBank); in applyMappingImpl()
2812 case AMDGPU::G_INSERT_VECTOR_ELT: { in applyMappingImpl()
2838 AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(3).getReg()); in applyMappingImpl()
2844 bool ShouldMoveIndexIntoLoop = IdxBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2899 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2900 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2901 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2932 case AMDGPU::G_AMDGPU_BUFFER_LOAD: in applyMappingImpl()
2933 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: in applyMappingImpl()
2934 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT: in applyMappingImpl()
2935 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: in applyMappingImpl()
2936 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE: in applyMappingImpl()
2937 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: in applyMappingImpl()
2938 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: in applyMappingImpl()
2939 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: in applyMappingImpl()
2940 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: in applyMappingImpl()
2941 case AMDGPU::G_AMDGPU_BUFFER_STORE: in applyMappingImpl()
2942 case AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE: in applyMappingImpl()
2943 case AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT: in applyMappingImpl()
2944 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT: in applyMappingImpl()
2945 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16: in applyMappingImpl()
2946 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT: in applyMappingImpl()
2947 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16: { in applyMappingImpl()
2952 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP: in applyMappingImpl()
2953 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD: in applyMappingImpl()
2954 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB: in applyMappingImpl()
2955 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN: in applyMappingImpl()
2956 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN: in applyMappingImpl()
2957 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX: in applyMappingImpl()
2958 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX: in applyMappingImpl()
2959 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND: in applyMappingImpl()
2960 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR: in applyMappingImpl()
2961 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR: in applyMappingImpl()
2962 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC: in applyMappingImpl()
2963 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: { in applyMappingImpl()
2968 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: in applyMappingImpl()
2969 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN: in applyMappingImpl()
2970 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: { in applyMappingImpl()
2975 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: { in applyMappingImpl()
2980 case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { in applyMappingImpl()
2984 case AMDGPU::G_INTRINSIC: { in applyMappingImpl()
3047 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD: in applyMappingImpl()
3048 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16: in applyMappingImpl()
3049 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: in applyMappingImpl()
3050 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: { in applyMappingImpl()
3051 const AMDGPU::RsrcIntrinsic *RSrcIntrin in applyMappingImpl()
3052 = AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID()); in applyMappingImpl()
3060 case AMDGPU::G_AMDGPU_INTRIN_BVH_INTERSECT_RAY: { in applyMappingImpl()
3066 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: { in applyMappingImpl()
3137 if (const AMDGPU::RsrcIntrinsic *RSrcIntrin = in applyMappingImpl()
3138 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in applyMappingImpl()
3153 case AMDGPU::G_SI_CALL: { in applyMappingImpl()
3164 unsigned FrameSetupOpcode = AMDGPU::ADJCALLSTACKUP; in applyMappingImpl()
3165 unsigned FrameDestroyOpcode = AMDGPU::ADJCALLSTACKDOWN; in applyMappingImpl()
3180 if (Start->getOpcode() == AMDGPU::COPY) { in applyMappingImpl()
3220 if (End->getOpcode() == AMDGPU::COPY) { in applyMappingImpl()
3248 case AMDGPU::G_LOAD: in applyMappingImpl()
3249 case AMDGPU::G_ZEXTLOAD: in applyMappingImpl()
3250 case AMDGPU::G_SEXTLOAD: { in applyMappingImpl()
3255 case AMDGPU::G_DYN_STACKALLOC: in applyMappingImpl()
3258 case AMDGPU::G_SBFX: in applyMappingImpl()
3261 case AMDGPU::G_UBFX: in applyMappingImpl()
3264 case AMDGPU::G_AMDGPU_MAD_U64_U32: in applyMappingImpl()
3265 case AMDGPU::G_AMDGPU_MAD_I64_I32: in applyMappingImpl()
3280 if (RB0 == AMDGPU::InvalidRegBankID) in regBankUnion()
3282 if (RB1 == AMDGPU::InvalidRegBankID) in regBankUnion()
3285 if (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) in regBankUnion()
3286 return AMDGPU::SGPRRegBankID; in regBankUnion()
3288 if (RB0 == AMDGPU::AGPRRegBankID && RB1 == AMDGPU::AGPRRegBankID) in regBankUnion()
3289 return AMDGPU::AGPRRegBankID; in regBankUnion()
3291 return AMDGPU::VGPRRegBankID; in regBankUnion()
3295 if (RB0 == AMDGPU::InvalidRegBankID) in regBankBoolUnion()
3297 if (RB1 == AMDGPU::InvalidRegBankID) in regBankBoolUnion()
3303 if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID) in regBankBoolUnion()
3304 return AMDGPU::VCCRegBankID; in regBankBoolUnion()
3312 unsigned RegBank = AMDGPU::InvalidRegBankID; in getMappingType()
3320 if (RegBank == AMDGPU::VGPRRegBankID) in getMappingType()
3336 if (Bank->getID() != AMDGPU::SGPRRegBankID) in isSALUMapping()
3355 OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getDefaultMappingSOP()
3377 unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID; in getDefaultMappingVOP()
3378 OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size); in getDefaultMappingVOP()
3397 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getDefaultMappingAllVGPR()
3436 unsigned NewBank = getRegBankID(OpReg, MRI, AMDGPU::SGPRRegBankID); in getImageMapping()
3437 OpdsMapping[I] = AMDGPU::getValueMapping(NewBank, Size); in getImageMapping()
3440 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getImageMapping()
3454 !AMDGPU::isFlatGlobalAddrSpace(PtrTy.getAddressSpace())) in getValueMappingForPtr()
3455 return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getValueMappingForPtr()
3460 return AMDGPU::getValueMapping(PtrBank->getID(), Size); in getValueMappingForPtr()
3480 if (PtrBank == &AMDGPU::SGPRRegBank && AMDGPU::isFlatGlobalAddrSpace(AS)) { in getInstrMappingForLoad()
3483 ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMappingForLoad()
3484 PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize); in getInstrMappingForLoad()
3486 ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMappingForLoad()
3491 AMDGPU::VGPRRegBankID : AMDGPU::SGPRRegBankID; in getInstrMappingForLoad()
3493 PtrMapping = AMDGPU::getValueMapping(PtrBankID, PtrSize); in getInstrMappingForLoad()
3496 ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMappingForLoad()
3497 PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize); in getInstrMappingForLoad()
3524 unsigned Bank = getRegBankID(Reg, MRI, AMDGPU::SGPRRegBankID); in getSGPROpMapping()
3526 return AMDGPU::getValueMapping(Bank, Size); in getSGPROpMapping()
3534 return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getVGPROpMapping()
3542 return AMDGPU::getValueMapping(AMDGPU::AGPRRegBankID, Size); in getAGPROpMapping()
3559 if (MI.isCopy() || MI.getOpcode() == AMDGPU::G_FREEZE) { in getInstrMapping()
3578 if (MI.getOpcode() == AMDGPU::G_FREEZE) in getInstrMapping()
3589 unsigned BankID = AMDGPU::SGPRRegBankID; in getInstrMapping()
3595 if (OpBank != AMDGPU::SGPRRegBankID) { in getInstrMapping()
3596 BankID = AMDGPU::VGPRRegBankID; in getInstrMapping()
3613 unsigned ResultBank = AMDGPU::InvalidRegBankID; in getInstrMapping()
3625 if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) { in getInstrMapping()
3626 ResultBank = AMDGPU::VGPRRegBankID; in getInstrMapping()
3635 assert(ResultBank != AMDGPU::InvalidRegBankID); in getInstrMapping()
3656 case AMDGPU::G_AND: in getInstrMapping()
3657 case AMDGPU::G_OR: in getInstrMapping()
3658 case AMDGPU::G_XOR: { in getInstrMapping()
3664 unsigned TargetBankID = AMDGPU::InvalidRegBankID; in getInstrMapping()
3665 unsigned BankLHS = AMDGPU::InvalidRegBankID; in getInstrMapping()
3666 unsigned BankRHS = AMDGPU::InvalidRegBankID; in getInstrMapping()
3669 if (DstBank == &AMDGPU::VCCRegBank) { in getInstrMapping()
3670 TargetBankID = AMDGPU::VCCRegBankID; in getInstrMapping()
3671 BankLHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3672 BankRHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3675 AMDGPU::SGPRRegBankID); in getInstrMapping()
3677 AMDGPU::SGPRRegBankID); in getInstrMapping()
3681 AMDGPU::VCCRegBankID); in getInstrMapping()
3683 AMDGPU::VCCRegBankID); in getInstrMapping()
3686 if (BankLHS == AMDGPU::VGPRRegBankID || BankRHS == AMDGPU::VGPRRegBankID) { in getInstrMapping()
3687 TargetBankID = AMDGPU::VGPRRegBankID; in getInstrMapping()
3688 } else if (BankLHS == AMDGPU::VCCRegBankID || BankRHS == AMDGPU::VCCRegBankID) { in getInstrMapping()
3689 TargetBankID = AMDGPU::VCCRegBankID; in getInstrMapping()
3690 BankLHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3691 BankRHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3692 } else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) { in getInstrMapping()
3693 TargetBankID = AMDGPU::SGPRRegBankID; in getInstrMapping()
3697 OpdsMapping[0] = AMDGPU::getValueMapping(TargetBankID, Size); in getInstrMapping()
3698 OpdsMapping[1] = AMDGPU::getValueMapping(BankLHS, Size); in getInstrMapping()
3699 OpdsMapping[2] = AMDGPU::getValueMapping(BankRHS, Size); in getInstrMapping()
3706 OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3709 OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3711 OpdsMapping[1] = AMDGPU::getValueMapping(Bank1, Size); in getInstrMapping()
3714 OpdsMapping[2] = AMDGPU::getValueMapping(Bank2, Size); in getInstrMapping()
3722 case AMDGPU::G_PTR_ADD: in getInstrMapping()
3723 case AMDGPU::G_PTRMASK: in getInstrMapping()
3724 case AMDGPU::G_ADD: in getInstrMapping()
3725 case AMDGPU::G_SUB: in getInstrMapping()
3726 case AMDGPU::G_MUL: in getInstrMapping()
3727 case AMDGPU::G_SHL: in getInstrMapping()
3728 case AMDGPU::G_LSHR: in getInstrMapping()
3729 case AMDGPU::G_ASHR: in getInstrMapping()
3730 case AMDGPU::G_UADDO: in getInstrMapping()
3731 case AMDGPU::G_USUBO: in getInstrMapping()
3732 case AMDGPU::G_UADDE: in getInstrMapping()
3733 case AMDGPU::G_SADDE: in getInstrMapping()
3734 case AMDGPU::G_USUBE: in getInstrMapping()
3735 case AMDGPU::G_SSUBE: in getInstrMapping()
3736 case AMDGPU::G_SMIN: in getInstrMapping()
3737 case AMDGPU::G_SMAX: in getInstrMapping()
3738 case AMDGPU::G_UMIN: in getInstrMapping()
3739 case AMDGPU::G_UMAX: in getInstrMapping()
3740 case AMDGPU::G_ABS: in getInstrMapping()
3741 case AMDGPU::G_SHUFFLE_VECTOR: in getInstrMapping()
3742 case AMDGPU::G_SBFX: in getInstrMapping()
3743 case AMDGPU::G_UBFX: in getInstrMapping()
3748 case AMDGPU::G_SADDSAT: // FIXME: Could lower sat ops for SALU in getInstrMapping()
3749 case AMDGPU::G_SSUBSAT: in getInstrMapping()
3750 case AMDGPU::G_UADDSAT: in getInstrMapping()
3751 case AMDGPU::G_USUBSAT: in getInstrMapping()
3752 case AMDGPU::G_FADD: in getInstrMapping()
3753 case AMDGPU::G_FSUB: in getInstrMapping()
3754 case AMDGPU::G_FPTOSI: in getInstrMapping()
3755 case AMDGPU::G_FPTOUI: in getInstrMapping()
3756 case AMDGPU::G_FMUL: in getInstrMapping()
3757 case AMDGPU::G_FMA: in getInstrMapping()
3758 case AMDGPU::G_FMAD: in getInstrMapping()
3759 case AMDGPU::G_FSQRT: in getInstrMapping()
3760 case AMDGPU::G_FFLOOR: in getInstrMapping()
3761 case AMDGPU::G_FCEIL: in getInstrMapping()
3762 case AMDGPU::G_FRINT: in getInstrMapping()
3763 case AMDGPU::G_SITOFP: in getInstrMapping()
3764 case AMDGPU::G_UITOFP: in getInstrMapping()
3765 case AMDGPU::G_FPTRUNC: in getInstrMapping()
3766 case AMDGPU::G_FPEXT: in getInstrMapping()
3767 case AMDGPU::G_FEXP2: in getInstrMapping()
3768 case AMDGPU::G_FLOG2: in getInstrMapping()
3769 case AMDGPU::G_FMINNUM: in getInstrMapping()
3770 case AMDGPU::G_FMAXNUM: in getInstrMapping()
3771 case AMDGPU::G_FMINNUM_IEEE: in getInstrMapping()
3772 case AMDGPU::G_FMAXNUM_IEEE: in getInstrMapping()
3773 case AMDGPU::G_FCANONICALIZE: in getInstrMapping()
3774 case AMDGPU::G_INTRINSIC_TRUNC: in getInstrMapping()
3775 case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar? in getInstrMapping()
3776 case AMDGPU::G_FSHR: // TODO: Expand for scalar in getInstrMapping()
3777 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in getInstrMapping()
3778 case AMDGPU::G_AMDGPU_FMAX_LEGACY: in getInstrMapping()
3779 case AMDGPU::G_AMDGPU_RCP_IFLAG: in getInstrMapping()
3780 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0: in getInstrMapping()
3781 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1: in getInstrMapping()
3782 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2: in getInstrMapping()
3783 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3: in getInstrMapping()
3784 case AMDGPU::G_AMDGPU_CVT_PK_I16_I32: in getInstrMapping()
3785 case AMDGPU::G_AMDGPU_SMED3: in getInstrMapping()
3787 case AMDGPU::G_UMULH: in getInstrMapping()
3788 case AMDGPU::G_SMULH: { in getInstrMapping()
3793 case AMDGPU::G_AMDGPU_MAD_U64_U32: in getInstrMapping()
3794 case AMDGPU::G_AMDGPU_MAD_I64_I32: { in getInstrMapping()
3808 if (Bank->getID() != AMDGPU::SGPRRegBankID) { in getInstrMapping()
3828 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64); in getInstrMapping()
3829 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
3830 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); in getInstrMapping()
3831 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); in getInstrMapping()
3832 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64); in getInstrMapping()
3835 case AMDGPU::G_IMPLICIT_DEF: { in getInstrMapping()
3837 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3840 case AMDGPU::G_FCONSTANT: in getInstrMapping()
3841 case AMDGPU::G_CONSTANT: in getInstrMapping()
3842 case AMDGPU::G_GLOBAL_VALUE: in getInstrMapping()
3843 case AMDGPU::G_BLOCK_ADDR: in getInstrMapping()
3844 case AMDGPU::G_READCYCLECOUNTER: { in getInstrMapping()
3846 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3849 case AMDGPU::G_FRAME_INDEX: { in getInstrMapping()
3853 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3856 case AMDGPU::G_DYN_STACKALLOC: { in getInstrMapping()
3858 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); in getInstrMapping()
3860 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBankID, 32); in getInstrMapping()
3863 case AMDGPU::G_AMDGPU_WAVE_ADDRESS: { in getInstrMapping()
3869 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
3870 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); in getInstrMapping()
3873 case AMDGPU::G_INSERT: { in getInstrMapping()
3878 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); in getInstrMapping()
3879 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); in getInstrMapping()
3880 OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize); in getInstrMapping()
3884 case AMDGPU::G_EXTRACT: { in getInstrMapping()
3888 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); in getInstrMapping()
3889 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); in getInstrMapping()
3893 case AMDGPU::G_BUILD_VECTOR: in getInstrMapping()
3894 case AMDGPU::G_BUILD_VECTOR_TRUNC: { in getInstrMapping()
3903 OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize); in getInstrMapping()
3904 OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize); in getInstrMapping()
3905 OpdsMapping[2] = AMDGPU::getValueMapping(Src1BankID, SrcSize); in getInstrMapping()
3911 case AMDGPU::G_MERGE_VALUES: in getInstrMapping()
3912 case AMDGPU::G_CONCAT_VECTORS: { in getInstrMapping()
3917 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
3920 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
3923 case AMDGPU::G_BITREVERSE: in getInstrMapping()
3924 case AMDGPU::G_BITCAST: in getInstrMapping()
3925 case AMDGPU::G_INTTOPTR: in getInstrMapping()
3926 case AMDGPU::G_PTRTOINT: in getInstrMapping()
3927 case AMDGPU::G_FABS: in getInstrMapping()
3928 case AMDGPU::G_FNEG: { in getInstrMapping()
3931 OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); in getInstrMapping()
3934 case AMDGPU::G_AMDGPU_FFBH_U32: in getInstrMapping()
3935 case AMDGPU::G_AMDGPU_FFBL_B32: in getInstrMapping()
3936 case AMDGPU::G_CTLZ_ZERO_UNDEF: in getInstrMapping()
3937 case AMDGPU::G_CTTZ_ZERO_UNDEF: { in getInstrMapping()
3940 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, 32); in getInstrMapping()
3941 OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(BankID, Size); in getInstrMapping()
3944 case AMDGPU::G_CTPOP: { in getInstrMapping()
3947 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, 32); in getInstrMapping()
3952 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); in getInstrMapping()
3955 case AMDGPU::G_TRUNC: { in getInstrMapping()
3961 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
3962 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
3965 case AMDGPU::G_ZEXT: in getInstrMapping()
3966 case AMDGPU::G_SEXT: in getInstrMapping()
3967 case AMDGPU::G_ANYEXT: in getInstrMapping()
3968 case AMDGPU::G_SEXT_INREG: { in getInstrMapping()
3978 case AMDGPU::SGPRRegBankID: in getInstrMapping()
3979 DstBank = AMDGPU::SGPRRegBankID; in getInstrMapping()
3982 DstBank = AMDGPU::VGPRRegBankID; in getInstrMapping()
3988 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize); in getInstrMapping()
3989 OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(), in getInstrMapping()
3993 case AMDGPU::G_FCMP: { in getInstrMapping()
3995 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
3997 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3998 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4001 case AMDGPU::G_STORE: { in getInstrMapping()
4008 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4013 case AMDGPU::G_ICMP: { in getInstrMapping()
4020 AMDGPU::SGPRRegBankID); in getInstrMapping()
4024 bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID && in getInstrMapping()
4025 Op2Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
4026 Op3Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
4031 DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
4032 unsigned SrcBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
4038 OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize); in getInstrMapping()
4039 OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, Size); in getInstrMapping()
4040 OpdsMapping[3] = AMDGPU::getValueMapping(SrcBank, Size); in getInstrMapping()
4043 case AMDGPU::G_EXTRACT_VECTOR_ELT: { in getInstrMapping()
4052 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(OutputBankID, DstSize); in getInstrMapping()
4053 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBankID, SrcSize); in getInstrMapping()
4056 OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
4059 case AMDGPU::G_INSERT_VECTOR_ELT: { in getInstrMapping()
4061 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
4069 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
4070 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
4074 if (InsertSize == 64 && OutputBankID == AMDGPU::VGPRRegBankID) { in getInstrMapping()
4075 OpdsMapping[2] = AMDGPU::getValueMappingSplit64(InsertEltBankID, in getInstrMapping()
4079 OpdsMapping[2] = AMDGPU::getValueMapping(InsertEltBankID, InsertSize); in getInstrMapping()
4083 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBankID, IdxSize); in getInstrMapping()
4086 case AMDGPU::G_UNMERGE_VALUES: { in getInstrMapping()
4093 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4097 case AMDGPU::G_AMDGPU_BUFFER_LOAD: in getInstrMapping()
4098 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: in getInstrMapping()
4099 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE: in getInstrMapping()
4100 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: in getInstrMapping()
4101 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT: in getInstrMapping()
4102 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: in getInstrMapping()
4103 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: in getInstrMapping()
4104 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: in getInstrMapping()
4105 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: in getInstrMapping()
4106 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT: in getInstrMapping()
4107 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16: in getInstrMapping()
4108 case AMDGPU::G_AMDGPU_BUFFER_STORE: in getInstrMapping()
4109 case AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE: in getInstrMapping()
4110 case AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT: in getInstrMapping()
4111 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT: in getInstrMapping()
4112 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16: { in getInstrMapping()
4131 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP: in getInstrMapping()
4132 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD: in getInstrMapping()
4133 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB: in getInstrMapping()
4134 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN: in getInstrMapping()
4135 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN: in getInstrMapping()
4136 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX: in getInstrMapping()
4137 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX: in getInstrMapping()
4138 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND: in getInstrMapping()
4139 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR: in getInstrMapping()
4140 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR: in getInstrMapping()
4141 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC: in getInstrMapping()
4142 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: in getInstrMapping()
4143 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: in getInstrMapping()
4144 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN: in getInstrMapping()
4145 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX: { in getInstrMapping()
4168 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: { in getInstrMapping()
4194 case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { in getInstrMapping()
4207 OpdsMapping[0] = AMDGPU::getValueMapping(ResultBank, Size0); in getInstrMapping()
4210 case AMDGPU::G_INTRINSIC: { in getInstrMapping()
4305 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4311 = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size); in getInstrMapping()
4315 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4321 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Dst0Size); in getInstrMapping()
4322 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Dst1Size); in getInstrMapping()
4325 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4326 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4335 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize); in getInstrMapping()
4336 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Src0Size); in getInstrMapping()
4337 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Src1Size); in getInstrMapping()
4344 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4346 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4347 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4354 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4355 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
4361 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4362 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4369 unsigned SrcBank = getRegBankID(SrcReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4372 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4373 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4377 OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, SrcSize); in getInstrMapping()
4378 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
4379 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4384 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4385 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4386 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4392 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4393 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4394 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4487 unsigned M0Bank = getRegBankID(M0Reg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4490 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4492 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4496 OpdsMapping[M0Idx] = AMDGPU::getValueMapping(M0Bank, 32); in getInstrMapping()
4504 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4505 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4506 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4507 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4513 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4514 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, SrcSize); in getInstrMapping()
4520 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD: in getInstrMapping()
4521 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD_D16: in getInstrMapping()
4522 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: in getInstrMapping()
4523 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE_D16: { in getInstrMapping()
4525 const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID); in getInstrMapping()
4533 case AMDGPU::G_AMDGPU_INTRIN_BVH_INTERSECT_RAY: { in getInstrMapping()
4535 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 128); in getInstrMapping()
4542 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4547 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4552 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: { in getInstrMapping()
4561 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4577 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4579 AMDGPU::SGPRRegBankID); in getInstrMapping()
4580 OpdsMapping[2] = AMDGPU::getValueMapping(M0Bank, 32); in getInstrMapping()
4581 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4587 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4592 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4593 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4597 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4598 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4599 OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4600 OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4603 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4604 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4605 OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4606 OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4613 AMDGPU::SGPRRegBankID); in getInstrMapping()
4614 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4620 AMDGPU::SGPRRegBankID); in getInstrMapping()
4621 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4626 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4631 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4632 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
4633 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
4637 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4642 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4699 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4705 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4709 AMDGPU::SGPRRegBankID); in getInstrMapping()
4710 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4718 AMDGPU::SGPRRegBankID); in getInstrMapping()
4719 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4730 unsigned M0Bank = getRegBankID(M0Reg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4733 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4735 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4739 OpdsMapping[M0Idx] = AMDGPU::getValueMapping(M0Bank, 32); in getInstrMapping()
4752 case AMDGPU::G_SELECT: { in getInstrMapping()
4755 AMDGPU::SGPRRegBankID); in getInstrMapping()
4757 AMDGPU::SGPRRegBankID); in getInstrMapping()
4758 bool SGPRSrcs = Op2Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
4759 Op3Bank == AMDGPU::SGPRRegBankID; in getInstrMapping()
4762 AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
4765 if (CondBank == AMDGPU::SGPRRegBankID) in getInstrMapping()
4766 CondBank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
4767 else if (CondBank == AMDGPU::VGPRRegBankID) in getInstrMapping()
4768 CondBank = AMDGPU::VCCRegBankID; in getInstrMapping()
4770 unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SGPRRegBankID ? in getInstrMapping()
4771 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
4773 assert(CondBank == AMDGPU::VCCRegBankID || CondBank == AMDGPU::SGPRRegBankID); in getInstrMapping()
4777 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4778 OpdsMapping[1] = AMDGPU::getValueMapping(CondBank, 1); in getInstrMapping()
4779 OpdsMapping[2] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4780 OpdsMapping[3] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4782 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4783 OpdsMapping[1] = AMDGPU::getValueMapping(CondBank, 1); in getInstrMapping()
4784 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4785 OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4791 case AMDGPU::G_SI_CALL: { in getInstrMapping()
4792 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64); in getInstrMapping()
4803 OpdsMapping[I] = AMDGPU::getValueMapping(OpBank, Size); in getInstrMapping()
4808 case AMDGPU::G_LOAD: in getInstrMapping()
4809 case AMDGPU::G_ZEXTLOAD: in getInstrMapping()
4810 case AMDGPU::G_SEXTLOAD: in getInstrMapping()
4813 case AMDGPU::G_ATOMICRMW_XCHG: in getInstrMapping()
4814 case AMDGPU::G_ATOMICRMW_ADD: in getInstrMapping()
4815 case AMDGPU::G_ATOMICRMW_SUB: in getInstrMapping()
4816 case AMDGPU::G_ATOMICRMW_AND: in getInstrMapping()
4817 case AMDGPU::G_ATOMICRMW_OR: in getInstrMapping()
4818 case AMDGPU::G_ATOMICRMW_XOR: in getInstrMapping()
4819 case AMDGPU::G_ATOMICRMW_MAX: in getInstrMapping()
4820 case AMDGPU::G_ATOMICRMW_MIN: in getInstrMapping()
4821 case AMDGPU::G_ATOMICRMW_UMAX: in getInstrMapping()
4822 case AMDGPU::G_ATOMICRMW_UMIN: in getInstrMapping()
4823 case AMDGPU::G_ATOMICRMW_FADD: in getInstrMapping()
4824 case AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG: in getInstrMapping()
4825 case AMDGPU::G_AMDGPU_ATOMIC_INC: in getInstrMapping()
4826 case AMDGPU::G_AMDGPU_ATOMIC_DEC: in getInstrMapping()
4827 case AMDGPU::G_AMDGPU_ATOMIC_FMIN: in getInstrMapping()
4828 case AMDGPU::G_AMDGPU_ATOMIC_FMAX: { in getInstrMapping()
4834 case AMDGPU::G_ATOMIC_CMPXCHG: { in getInstrMapping()
4841 case AMDGPU::G_BRCOND: { in getInstrMapping()
4843 AMDGPU::SGPRRegBankID); in getInstrMapping()
4845 if (Bank != AMDGPU::SGPRRegBankID) in getInstrMapping()
4846 Bank = AMDGPU::VCCRegBankID; in getInstrMapping()
4848 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1); in getInstrMapping()
4851 case AMDGPU::G_FPTRUNC_ROUND_UPWARD: in getInstrMapping()
4852 case AMDGPU::G_FPTRUNC_ROUND_DOWNWARD: in getInstrMapping()