Lines Matching refs:AMDGPU
95 case AMDGPU::COPY: in isCopyFromExec()
96 case AMDGPU::S_MOV_B64: in isCopyFromExec()
97 case AMDGPU::S_MOV_B64_term: in isCopyFromExec()
98 case AMDGPU::S_MOV_B32: in isCopyFromExec()
99 case AMDGPU::S_MOV_B32_term: { in isCopyFromExec()
106 return AMDGPU::NoRegister; in isCopyFromExec()
112 case AMDGPU::COPY: in isCopyToExec()
113 case AMDGPU::S_MOV_B64: in isCopyToExec()
114 case AMDGPU::S_MOV_B32: { in isCopyToExec()
120 case AMDGPU::S_MOV_B64_term: in isCopyToExec()
121 case AMDGPU::S_MOV_B32_term: in isCopyToExec()
132 case AMDGPU::S_AND_B64: in isLogicalOpOnExec()
133 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
134 case AMDGPU::S_XOR_B64: in isLogicalOpOnExec()
135 case AMDGPU::S_ANDN2_B64: in isLogicalOpOnExec()
136 case AMDGPU::S_ORN2_B64: in isLogicalOpOnExec()
137 case AMDGPU::S_NAND_B64: in isLogicalOpOnExec()
138 case AMDGPU::S_NOR_B64: in isLogicalOpOnExec()
139 case AMDGPU::S_XNOR_B64: { in isLogicalOpOnExec()
141 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
144 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
148 case AMDGPU::S_AND_B32: in isLogicalOpOnExec()
149 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
150 case AMDGPU::S_XOR_B32: in isLogicalOpOnExec()
151 case AMDGPU::S_ANDN2_B32: in isLogicalOpOnExec()
152 case AMDGPU::S_ORN2_B32: in isLogicalOpOnExec()
153 case AMDGPU::S_NAND_B32: in isLogicalOpOnExec()
154 case AMDGPU::S_NOR_B32: in isLogicalOpOnExec()
155 case AMDGPU::S_XNOR_B32: { in isLogicalOpOnExec()
157 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
160 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
166 return AMDGPU::NoRegister; in isLogicalOpOnExec()
171 case AMDGPU::S_AND_B64: in getSaveExecOp()
172 return AMDGPU::S_AND_SAVEEXEC_B64; in getSaveExecOp()
173 case AMDGPU::S_OR_B64: in getSaveExecOp()
174 return AMDGPU::S_OR_SAVEEXEC_B64; in getSaveExecOp()
175 case AMDGPU::S_XOR_B64: in getSaveExecOp()
176 return AMDGPU::S_XOR_SAVEEXEC_B64; in getSaveExecOp()
177 case AMDGPU::S_ANDN2_B64: in getSaveExecOp()
178 return AMDGPU::S_ANDN2_SAVEEXEC_B64; in getSaveExecOp()
179 case AMDGPU::S_ORN2_B64: in getSaveExecOp()
180 return AMDGPU::S_ORN2_SAVEEXEC_B64; in getSaveExecOp()
181 case AMDGPU::S_NAND_B64: in getSaveExecOp()
182 return AMDGPU::S_NAND_SAVEEXEC_B64; in getSaveExecOp()
183 case AMDGPU::S_NOR_B64: in getSaveExecOp()
184 return AMDGPU::S_NOR_SAVEEXEC_B64; in getSaveExecOp()
185 case AMDGPU::S_XNOR_B64: in getSaveExecOp()
186 return AMDGPU::S_XNOR_SAVEEXEC_B64; in getSaveExecOp()
187 case AMDGPU::S_AND_B32: in getSaveExecOp()
188 return AMDGPU::S_AND_SAVEEXEC_B32; in getSaveExecOp()
189 case AMDGPU::S_OR_B32: in getSaveExecOp()
190 return AMDGPU::S_OR_SAVEEXEC_B32; in getSaveExecOp()
191 case AMDGPU::S_XOR_B32: in getSaveExecOp()
192 return AMDGPU::S_XOR_SAVEEXEC_B32; in getSaveExecOp()
193 case AMDGPU::S_ANDN2_B32: in getSaveExecOp()
194 return AMDGPU::S_ANDN2_SAVEEXEC_B32; in getSaveExecOp()
195 case AMDGPU::S_ORN2_B32: in getSaveExecOp()
196 return AMDGPU::S_ORN2_SAVEEXEC_B32; in getSaveExecOp()
197 case AMDGPU::S_NAND_B32: in getSaveExecOp()
198 return AMDGPU::S_NAND_SAVEEXEC_B32; in getSaveExecOp()
199 case AMDGPU::S_NOR_B32: in getSaveExecOp()
200 return AMDGPU::S_NOR_SAVEEXEC_B32; in getSaveExecOp()
201 case AMDGPU::S_XNOR_B32: in getSaveExecOp()
202 return AMDGPU::S_XNOR_SAVEEXEC_B32; in getSaveExecOp()
204 return AMDGPU::INSTRUCTION_LIST_END; in getSaveExecOp()
212 case AMDGPU::S_MOV_B32_term: { in removeTerminatorBit()
214 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
217 case AMDGPU::S_MOV_B64_term: { in removeTerminatorBit()
219 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
222 case AMDGPU::S_XOR_B64_term: { in removeTerminatorBit()
225 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
228 case AMDGPU::S_XOR_B32_term: { in removeTerminatorBit()
231 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
234 case AMDGPU::S_OR_B64_term: { in removeTerminatorBit()
237 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
240 case AMDGPU::S_OR_B32_term: { in removeTerminatorBit()
243 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
246 case AMDGPU::S_ANDN2_B64_term: { in removeTerminatorBit()
249 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
252 case AMDGPU::S_ANDN2_B32_term: { in removeTerminatorBit()
255 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
258 case AMDGPU::S_AND_B64_term: { in removeTerminatorBit()
261 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
264 case AMDGPU::S_AND_B32_term: { in removeTerminatorBit()
267 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
482 if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END) in optimizeExecSequence()
547 OtherInst->substituteRegister(CopyToExec, Exec, AMDGPU::NoSubRegister, in optimizeExecSequence()
561 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence()
566 MachineOperand *Src0 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src0); in optimizeVCMPSaveExecSequence()
567 MachineOperand *Src1 = TII->getNamedOperand(VCmp, AMDGPU::OpName::src1); in optimizeVCMPSaveExecSequence()
574 unsigned MovOpcode = IsSGPR32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVCMPSaveExecSequence()
591 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::src0_modifiers); in optimizeVCMPSaveExecSequence()
594 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::src1_modifiers); in optimizeVCMPSaveExecSequence()
597 TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::clamp); in optimizeVCMPSaveExecSequence()
624 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
633 MachineOperand *SaveExecSrc0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
649 return AMDGPU::getVCMPXOpFromVCMP(Check->getOpcode()) != -1 && in tryRecordVCmpxAndSaveexecSequence()
657 MachineOperand *VCmpDest = TII->getNamedOperand(*VCmp, AMDGPU::OpName::sdst); in tryRecordVCmpxAndSaveexecSequence()
661 MachineOperand *Src0 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src0); in tryRecordVCmpxAndSaveexecSequence()
666 MachineOperand *Src1 = TII->getNamedOperand(*VCmp, AMDGPU::OpName::src1); in tryRecordVCmpxAndSaveexecSequence()
710 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
721 ? AMDGPU::S_OR_SAVEEXEC_B32 in tryRecordOrSaveexecXorSequence()
722 : AMDGPU::S_OR_SAVEEXEC_B64; in tryRecordOrSaveexecXorSequence()
748 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
749 : AMDGPU::S_ANDN2_SAVEEXEC_B64; in optimizeOrSaveexecXorSequences()