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Searched refs:ARM (Results 1 – 25 of 776) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1405 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1406 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV8()
1499 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1500 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV81()
1994 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
2204 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2237 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2238 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2239 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2444 ARM::t2BICri : ARM::BICri; in ExpandMI()
[all …]
H A DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
42 case ARM::tMUL: in isV8EligibleForIT()
43 case ARM::tMVN: in isV8EligibleForIT()
44 case ARM::tORR: in isV8EligibleForIT()
45 case ARM::tROR: in isV8EligibleForIT()
46 case ARM::tRSB: in isV8EligibleForIT()
47 case ARM::tSBC: in isV8EligibleForIT()
[all …]
H A DARMFixCortexA57AES1742098Pass.cpp129 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
145 case ARM::AESD: in isSafeAESInput()
146 case ARM::AESE: in isSafeAESInput()
147 case ARM::AESMC: in isSafeAESInput()
152 case ARM::VANDd: in isSafeAESInput()
153 case ARM::VANDq: in isSafeAESInput()
154 case ARM::VORRd: in isSafeAESInput()
155 case ARM::VORRq: in isSafeAESInput()
156 case ARM::VEORd: in isSafeAESInput()
157 case ARM::VEORq: in isSafeAESInput()
[all …]
H A DARMRegisterBankInfo.cpp30 namespace ARM { namespace
240 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
241 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
262 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
276 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] in getInstrMapping()
288 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
298 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
299 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; in getInstrMapping()
384 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
385 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
[all …]
H A DARMBaseInstrInfo.cpp505 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); in insertBranch()
2432 {ARM::ADDSri, ARM::ADDri},
2433 {ARM::ADDSrr, ARM::ADDrr},
2434 {ARM::ADDSrsi, ARM::ADDrsi},
2435 {ARM::ADDSrsr, ARM::ADDrsr},
2437 {ARM::SUBSri, ARM::SUBri},
2438 {ARM::SUBSrr, ARM::SUBrr},
2442 {ARM::RSBSri, ARM::RSBri},
2449 {ARM::tADCS, ARM::tADC},
2454 {ARM::tSBCS, ARM::tSBC},
[all …]
H A DThumb2SizeReduction.cpp85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
119 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
121 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
132 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
141 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
151 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
266 case ARM::tMUL: in isHighLatencyCPSR()
394 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
[all …]
H A DThumb2InstrInfo.cpp421 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
426 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
429 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
431 case ARM::t2PLIi12: return ARM::t2PLIi8; in negativeOffsetOpcode()
455 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
460 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
463 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
489 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
494 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
497 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
[all …]
H A DARMInstrInfo.cpp61 case ARM::LDRH_PRE: in getUnindexedOpcode()
62 case ARM::LDRH_POST: in getUnindexedOpcode()
63 return ARM::LDRH; in getUnindexedOpcode()
69 case ARM::LDRSH_PRE: in getUnindexedOpcode()
80 case ARM::STRH_PRE: in getUnindexedOpcode()
82 return ARM::STRH; in getUnindexedOpcode()
100 expandLoadStackGuardBase(MI, ARM::MRC, ARM::LDRi12); in expandLoadStackGuard()
109 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12); in expandLoadStackGuard()
111 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12); in expandLoadStackGuard()
116 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12); in expandLoadStackGuard()
[all …]
H A DARMBaseInstrInfo.h564 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
640 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
644 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 || in isJumpTableBranchOpcode()
645 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr || in isJumpTableBranchOpcode()
651 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
717 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || in isPopOpcode()
722 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || in isPushOpcode()
728 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 || in isSubImmOpcode()
729 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 || in isSubImmOpcode()
730 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri; in isSubImmOpcode()
[all …]
H A DARMLoadStoreOptimizer.cpp501 Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; in UpdateBaseRegUses()
503 Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi; in UpdateBaseRegUses()
1039 if (PReg == ARM::SP || PReg == ARM::PC) in FormCandidates()
1065 if (Reg == ARM::SP || Reg == ARM::PC) in FormCandidates()
1639 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE; in MergeBaseUpdateLSDouble()
1644 NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST; in MergeBaseUpdateLSDouble()
1766 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1831 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1832 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1836 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
[all …]
H A DMVETailPredUtils.h30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
[all …]
H A DARMISelDAGToDAG.cpp3575 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
4107 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
4447 ARM::VLD2d8wb_fixed, ARM::VLD2d16wb_fixed, ARM::VLD2d32wb_fixed, in Select()
4484 ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, in Select()
4512 ARM::VLD1q8wb_fixed, ARM::VLD1q16wb_fixed, ARM::VLD1q32wb_fixed, in Select()
4603 ARM::VST2d8wb_fixed, ARM::VST2d16wb_fixed, ARM::VST2d32wb_fixed, in Select()
4632 ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD, ARM::VST4d32Pseudo_UPD, in Select()
5301 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5311 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5321 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
[all …]
H A DARMTargetTransformInfo.h72 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
74 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
75 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
78 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
79 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
91 ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
92 ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
93 ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
[all …]
H A DARMAsmPrinter.cpp1496 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1684 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1685 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1686 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1687 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1688 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1689 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1690 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1691 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1752 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DARMTargetParser.def91 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
95 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
99 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
100 ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
103 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
107 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
112 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
127 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
133 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
138 (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
[all …]
/llvm-project-15.0.7/llvm/unittests/Support/
H A DTargetParserTest.cpp204 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
209 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
214 ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
255 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
260 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
265 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
270 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
276 ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
813 EXPECT_EQ(ARM::ISAKind::ARM, ARM::parseArchISA(arm_1)); in TEST()
814 EXPECT_EQ(ARM::ISAKind::ARM, ARM::parseArchISA(arm_2)); in TEST()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dsegmented-stacks.ll17 ; ARM-linux-LABEL: test_basic:
21 ; ARM-linux-NEXT: mov r5, sp
23 ; ARM-linux-NEXT: cmp r4, r5
27 ; ARM-linux-NEXT: mov r5, #0
32 ; ARM-linux-NEXT: bx lr
51 ; ARM-android-NEXT: bx lr
79 ; ARM-linux-NEXT: bx lr
125 ; ARM-linux-NEXT: bx lr
129 ; ARM-linux: .LCPI2_0:
177 ; ARM-linux-NEXT: bx lr
[all …]
H A Ddebug-frame-large-stack.ll9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
24 ; CHECK-ARM-LABEL: test2:
25 ; CHECK-ARM: .cfi_startproc
28 ; CHECK-ARM: .cfi_offset lr, -4
36 ; CHECK-ARM: .cfi_endproc
59 ; CHECK-ARM-LABEL: test3:
60 ; CHECK-ARM: .cfi_startproc
[all …]
H A Dtwo-part-imm.ll9 ; CHECK-ARM-LABEL: sub0:
10 ; CHECK-ARM: @ %bb.0:
23 ; CHECK-ARM-LABEL: sub1:
24 ; CHECK-ARM: @ %bb.0:
29 ; CHECK-ARM-NEXT: @ %bb.1:
44 ; CHECK-ARM-LABEL: sub2:
60 ; CHECK-ARM-LABEL: sub3:
81 ; CHECK-ARM-LABEL: sub4:
101 ; CHECK-ARM-LABEL: add0:
115 ; CHECK-ARM-LABEL: add1:
[all …]
H A Darm-shrink-wrapping.ll64 ; ARM-ENABLE-LABEL: foo:
65 ; ARM-ENABLE: @ %bb.0:
78 ; ARM-ENABLE-NEXT: bx lr
80 ; ARM-DISABLE-LABEL: foo:
202 ; ARM-ENABLE-NEXT: nop
355 ; ARM-NEXT: mov r0, #0
358 ; ARM-NEXT: nop
370 ; ARM-NEXT: nop
897 ; ARM-NEXT: bx lr
1375 ; ARM-NEXT: b LBB9_2
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp147 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
189 emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM); in emitTargetAttributes()
233 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16 in emitTargetAttributes()
247 : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16 in emitTargetAttributes()
251 ? ARM::FK_VFPV4 in emitTargetAttributes()
252 : (STI.hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16 in emitTargetAttributes()
258 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16 in emitTargetAttributes()
265 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16 in emitTargetAttributes()
268 emitFPU(ARM::FK_VFPV2); in emitTargetAttributes()
272 if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64)) in emitTargetAttributes()
[all …]
H A DARMAsmBackend.cpp216 case ARM::tBcc: in getRelaxedOpcode()
218 case ARM::tLDRpci: in getRelaxedOpcode()
220 case ARM::tADR: in getRelaxedOpcode()
222 case ARM::tB: in getRelaxedOpcode()
224 case ARM::tCBZ: in getRelaxedOpcode()
225 return ARM::tHINT; in getRelaxedOpcode()
226 case ARM::tCBNZ: in getRelaxedOpcode()
227 return ARM::tHINT; in getRelaxedOpcode()
300 case ARM::fixup_wls: in reasonForFixupRelaxation()
302 case ARM::fixup_le: in reasonForFixupRelaxation()
[all …]
H A DARMMCTargetDesc.cpp118 case ARM::LR: in getARMLoadDeprecationInfo()
121 case ARM::PC: in getARMLoadDeprecationInfo()
145 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
199 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
230 {codeview::RegisterId::ARM_R0, ARM::R0}, in initLLVMToCVRegMapping()
231 {codeview::RegisterId::ARM_R1, ARM::R1}, in initLLVMToCVRegMapping()
232 {codeview::RegisterId::ARM_R2, ARM::R2}, in initLLVMToCVRegMapping()
233 {codeview::RegisterId::ARM_R3, ARM::R3}, in initLLVMToCVRegMapping()
234 {codeview::RegisterId::ARM_R4, ARM::R4}, in initLLVMToCVRegMapping()
235 {codeview::RegisterId::ARM_R5, ARM::R5}, in initLLVMToCVRegMapping()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1283 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1284 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1285 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1286 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1290 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1291 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1292 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1591 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dsegmented-stacks.ll38 ; ARM-LABEL: test_basic:
39 ; ARM: @ %bb.0:
42 ; ARM-NEXT: mov r5, sp
44 ; ARM-NEXT: cmp r4, r5
46 ; ARM-NEXT: @ %bb.1:
48 ; ARM-NEXT: mov r5, #0
53 ; ARM-NEXT: bx lr
54 ; ARM-NEXT: .LBB0_2:
58 ; ARM-NEXT: .pad #40
60 ; ARM-NEXT: mov r0, sp
[all …]

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