Lines Matching refs:ARM
30 namespace ARM { namespace
141 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
143 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
146 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
148 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
161 ARM::tGPREven_and_GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
163 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
168 ARM::checkPartialMappings(); in ARMRegisterBankInfo()
169 ARM::checkValueMappings(); in ARMRegisterBankInfo()
179 using namespace ARM; in getRegBankFromRegClass()
199 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
206 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
231 const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
240 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
241 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
262 OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
276 ? &ARM::ValueMappings[ARM::GPR3OpsIdx] in getInstrMapping()
277 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
278 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); in getInstrMapping()
286 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
287 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) in getInstrMapping()
288 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
298 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
299 : &ARM::ValueMappings[ARM::SPR3OpsIdx]; in getInstrMapping()
306 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
307 &ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
308 &ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
309 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) in getInstrMapping()
310 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
311 &ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
312 &ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
313 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); in getInstrMapping()
321 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
322 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); in getInstrMapping()
330 getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
331 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); in getInstrMapping()
342 ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
343 &ARM::ValueMappings[ARM::DPR3OpsIdx]}) in getInstrMapping()
344 : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
345 &ARM::ValueMappings[ARM::SPR3OpsIdx]}); in getInstrMapping()
356 ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
357 &ARM::ValueMappings[ARM::GPR3OpsIdx]}) in getInstrMapping()
358 : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
359 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); in getInstrMapping()
365 {Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
366 : &ARM::ValueMappings[ARM::SPR3OpsIdx], in getInstrMapping()
374 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); in getInstrMapping()
384 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
385 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
386 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
387 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); in getInstrMapping()
395 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, in getInstrMapping()
396 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
397 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); in getInstrMapping()
413 auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx] in getInstrMapping()
414 : &ARM::ValueMappings[ARM::DPR3OpsIdx]; in getInstrMapping()
416 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, in getInstrMapping()
430 getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx], in getInstrMapping()
431 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
432 &ARM::ValueMappings[ARM::GPR3OpsIdx]}); in getInstrMapping()
445 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
446 &ARM::ValueMappings[ARM::GPR3OpsIdx], in getInstrMapping()
447 &ARM::ValueMappings[ARM::DPR3OpsIdx]}); in getInstrMapping()
455 getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr}); in getInstrMapping()
464 OperandBanks[0] = Size == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] in getInstrMapping()
465 : &ARM::ValueMappings[ARM::GPR3OpsIdx]; in getInstrMapping()
478 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()