Lines Matching refs:ARM
84 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
88 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
89 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
91 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
92 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
95 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
96 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
97 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
98 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
101 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
102 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
103 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
104 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
105 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
106 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
108 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
109 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
110 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
111 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
112 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
113 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
114 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
115 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
116 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
118 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
119 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
120 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
121 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
122 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
123 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
124 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
125 { ARM::t2TEQrr, ARM::tEOR, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
126 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
127 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
128 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
132 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
133 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
134 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
135 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
136 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
137 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
138 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
139 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
140 { ARM::t2LDR_POST,ARM::tLDMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
141 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
142 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
143 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
144 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
145 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
146 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
147 { ARM::t2STR_POST,ARM::tSTMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
149 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
150 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
151 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
155 { ARM::t2STMIA, ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
156 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
157 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
257 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
265 case ARM::FMSTAT: in isHighLatencyCPSR()
266 case ARM::tMUL: in isHighLatencyCPSR()
305 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
324 if (Use->getOpcode() == ARM::t2MOVi || in canAddPseudoFlagDep()
325 Use->getOpcode() == ARM::t2MOVi16) in canAddPseudoFlagDep()
377 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD); in VerifyLowRegs()
378 bool isLROk = (Opc == ARM::t2STMDB_UPD); in VerifyLowRegs()
385 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
387 if (isPCOk && Reg == ARM::PC) in VerifyLowRegs()
389 if (isLROk && Reg == ARM::LR) in VerifyLowRegs()
391 if (Reg == ARM::SP) { in VerifyLowRegs()
394 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs()
422 case ARM::t2LDRi12: in ReduceLoadStore()
423 case ARM::t2STRi12: in ReduceLoadStore()
424 if (MI->getOperand(1).getReg() == ARM::SP) { in ReduceLoadStore()
433 case ARM::t2LDRBi12: in ReduceLoadStore()
434 case ARM::t2STRBi12: in ReduceLoadStore()
438 case ARM::t2LDRHi12: in ReduceLoadStore()
439 case ARM::t2STRHi12: in ReduceLoadStore()
444 case ARM::t2LDRs: in ReduceLoadStore()
445 case ARM::t2LDRBs: in ReduceLoadStore()
446 case ARM::t2LDRHs: in ReduceLoadStore()
447 case ARM::t2LDRSBs: in ReduceLoadStore()
448 case ARM::t2LDRSHs: in ReduceLoadStore()
449 case ARM::t2STRs: in ReduceLoadStore()
450 case ARM::t2STRBs: in ReduceLoadStore()
451 case ARM::t2STRHs: in ReduceLoadStore()
455 case ARM::t2LDR_POST: in ReduceLoadStore()
456 case ARM::t2STR_POST: { in ReduceLoadStore()
467 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore()
499 case ARM::t2LDMIA: { in ReduceLoadStore()
520 case ARM::t2STMIA: { in ReduceLoadStore()
537 case ARM::t2LDMIA_RET: { in ReduceLoadStore()
539 if (BaseReg != ARM::SP) in ReduceLoadStore()
546 case ARM::t2LDMIA_UPD: in ReduceLoadStore()
547 case ARM::t2STMIA_UPD: in ReduceLoadStore()
548 case ARM::t2STMDB_UPD: { in ReduceLoadStore()
552 if (BaseReg == ARM::SP && in ReduceLoadStore()
553 (Entry.WideOpc == ARM::t2LDMIA_UPD || in ReduceLoadStore()
554 Entry.WideOpc == ARM::t2STMDB_UPD)) { in ReduceLoadStore()
558 (Entry.WideOpc != ARM::t2LDMIA_UPD && in ReduceLoadStore()
559 Entry.WideOpc != ARM::t2STMIA_UPD)) { in ReduceLoadStore()
597 if (Entry.WideOpc == ARM::t2STMIA) in ReduceLoadStore()
637 if (Opc == ARM::t2ADDri) { in ReduceSpecial()
640 if (MI->getOperand(1).getReg() != ARM::SP) { in ReduceSpecial()
658 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
663 TII->get(ARM::tADDrSPi)) in ReduceSpecial()
688 case ARM::t2ADDSri: in ReduceSpecial()
689 case ARM::t2ADDSrr: { in ReduceSpecial()
694 case ARM::t2ADDSri: in ReduceSpecial()
698 case ARM::t2ADDSrr: in ReduceSpecial()
704 case ARM::t2RSBri: in ReduceSpecial()
705 case ARM::t2RSBSri: in ReduceSpecial()
706 case ARM::t2SXTB: in ReduceSpecial()
707 case ARM::t2SXTH: in ReduceSpecial()
708 case ARM::t2UXTB: in ReduceSpecial()
709 case ARM::t2UXTH: in ReduceSpecial()
713 case ARM::t2MOVi16: in ReduceSpecial()
719 case ARM::t2CMPrr: { in ReduceSpecial()
726 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 }; in ReduceSpecial()
731 case ARM::t2TEQrr: { in ReduceSpecial()
760 if (MI->getOpcode() == ARM::t2MUL) { in ReduceTo2Addr()
819 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
883 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
911 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
931 if (MCID.getOpcode() == ARM::t2TEQrr) { in ReduceToNarrow()
951 if ((MCID.getOpcode() == ARM::t2RSBSri || in ReduceToNarrow()
952 MCID.getOpcode() == ARM::t2RSBri || in ReduceToNarrow()
953 MCID.getOpcode() == ARM::t2SXTB || in ReduceToNarrow()
954 MCID.getOpcode() == ARM::t2SXTH || in ReduceToNarrow()
955 MCID.getOpcode() == ARM::t2UXTB || in ReduceToNarrow()
956 MCID.getOpcode() == ARM::t2UXTH) && i == 2) in ReduceToNarrow()
963 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
988 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
1003 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
1049 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); in ReduceMBB()
1104 if (BundleMI->killsRegister(ARM::CPSR)) in ReduceMBB()
1106 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR); in ReduceMBB()
1109 MO = BundleMI->findRegisterUseOperand(ARM::CPSR); in ReduceMBB()