Lines Matching refs:ARM
53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
92 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
177 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
178 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
193 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
196 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
197 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
198 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
219 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
220 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
228 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
234 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
237 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot()
238 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
239 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
256 expandLoadStackGuardBase(MI, ARM::t2MRC, ARM::t2LDRi12); in expandLoadStackGuard()
264 expandLoadStackGuardBase(MI, ARM::t2LDRLIT_ga_pcrel, ARM::t2LDRi12); in expandLoadStackGuard()
266 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12); in expandLoadStackGuard()
268 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12); in expandLoadStackGuard()
276 case ARM::MVE_VMAXNMAf16: in commuteInstructionImpl()
277 case ARM::MVE_VMAXNMAf32: in commuteInstructionImpl()
278 case ARM::MVE_VMINNMAf16: in commuteInstructionImpl()
279 case ARM::MVE_VMINNMAf32: in commuteInstructionImpl()
295 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
306 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
312 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
318 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) in emitT2RegPlusImmediate()
327 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) in emitT2RegPlusImmediate()
339 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) in emitT2RegPlusImmediate()
353 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
355 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) in emitT2RegPlusImmediate()
359 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
363 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
367 if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) { in emitT2RegPlusImmediate()
369 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
379 bool ToSP = DestReg == ARM::SP; in emitT2RegPlusImmediate()
380 unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri; in emitT2RegPlusImmediate()
381 unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri; in emitT2RegPlusImmediate()
382 unsigned t2SUBi12 = ToSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12; in emitT2RegPlusImmediate()
383 unsigned t2ADDi12 = ToSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in emitT2RegPlusImmediate()
421 case ARM::t2LDRi12: return ARM::t2LDRi8; in negativeOffsetOpcode()
422 case ARM::t2LDRHi12: return ARM::t2LDRHi8; in negativeOffsetOpcode()
423 case ARM::t2LDRBi12: return ARM::t2LDRBi8; in negativeOffsetOpcode()
424 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; in negativeOffsetOpcode()
425 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; in negativeOffsetOpcode()
426 case ARM::t2STRi12: return ARM::t2STRi8; in negativeOffsetOpcode()
427 case ARM::t2STRBi12: return ARM::t2STRBi8; in negativeOffsetOpcode()
428 case ARM::t2STRHi12: return ARM::t2STRHi8; in negativeOffsetOpcode()
429 case ARM::t2PLDi12: return ARM::t2PLDi8; in negativeOffsetOpcode()
430 case ARM::t2PLDWi12: return ARM::t2PLDWi8; in negativeOffsetOpcode()
431 case ARM::t2PLIi12: return ARM::t2PLIi8; in negativeOffsetOpcode()
433 case ARM::t2LDRi8: in negativeOffsetOpcode()
434 case ARM::t2LDRHi8: in negativeOffsetOpcode()
435 case ARM::t2LDRBi8: in negativeOffsetOpcode()
436 case ARM::t2LDRSHi8: in negativeOffsetOpcode()
437 case ARM::t2LDRSBi8: in negativeOffsetOpcode()
438 case ARM::t2STRi8: in negativeOffsetOpcode()
439 case ARM::t2STRBi8: in negativeOffsetOpcode()
440 case ARM::t2STRHi8: in negativeOffsetOpcode()
441 case ARM::t2PLDi8: in negativeOffsetOpcode()
442 case ARM::t2PLDWi8: in negativeOffsetOpcode()
443 case ARM::t2PLIi8: in negativeOffsetOpcode()
455 case ARM::t2LDRi8: return ARM::t2LDRi12; in positiveOffsetOpcode()
456 case ARM::t2LDRHi8: return ARM::t2LDRHi12; in positiveOffsetOpcode()
457 case ARM::t2LDRBi8: return ARM::t2LDRBi12; in positiveOffsetOpcode()
458 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; in positiveOffsetOpcode()
459 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; in positiveOffsetOpcode()
460 case ARM::t2STRi8: return ARM::t2STRi12; in positiveOffsetOpcode()
461 case ARM::t2STRBi8: return ARM::t2STRBi12; in positiveOffsetOpcode()
462 case ARM::t2STRHi8: return ARM::t2STRHi12; in positiveOffsetOpcode()
463 case ARM::t2PLDi8: return ARM::t2PLDi12; in positiveOffsetOpcode()
464 case ARM::t2PLDWi8: return ARM::t2PLDWi12; in positiveOffsetOpcode()
465 case ARM::t2PLIi8: return ARM::t2PLIi12; in positiveOffsetOpcode()
467 case ARM::t2LDRi12: in positiveOffsetOpcode()
468 case ARM::t2LDRHi12: in positiveOffsetOpcode()
469 case ARM::t2LDRBi12: in positiveOffsetOpcode()
470 case ARM::t2LDRSHi12: in positiveOffsetOpcode()
471 case ARM::t2LDRSBi12: in positiveOffsetOpcode()
472 case ARM::t2STRi12: in positiveOffsetOpcode()
473 case ARM::t2STRBi12: in positiveOffsetOpcode()
474 case ARM::t2STRHi12: in positiveOffsetOpcode()
475 case ARM::t2PLDi12: in positiveOffsetOpcode()
476 case ARM::t2PLDWi12: in positiveOffsetOpcode()
477 case ARM::t2PLIi12: in positiveOffsetOpcode()
489 case ARM::t2LDRs: return ARM::t2LDRi12; in immediateOffsetOpcode()
490 case ARM::t2LDRHs: return ARM::t2LDRHi12; in immediateOffsetOpcode()
491 case ARM::t2LDRBs: return ARM::t2LDRBi12; in immediateOffsetOpcode()
492 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; in immediateOffsetOpcode()
493 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; in immediateOffsetOpcode()
494 case ARM::t2STRs: return ARM::t2STRi12; in immediateOffsetOpcode()
495 case ARM::t2STRBs: return ARM::t2STRBi12; in immediateOffsetOpcode()
496 case ARM::t2STRHs: return ARM::t2STRHi12; in immediateOffsetOpcode()
497 case ARM::t2PLDs: return ARM::t2PLDi12; in immediateOffsetOpcode()
498 case ARM::t2PLDWs: return ARM::t2PLDWi12; in immediateOffsetOpcode()
499 case ARM::t2PLIs: return ARM::t2PLIi12; in immediateOffsetOpcode()
501 case ARM::t2LDRi12: in immediateOffsetOpcode()
502 case ARM::t2LDRHi12: in immediateOffsetOpcode()
503 case ARM::t2LDRBi12: in immediateOffsetOpcode()
504 case ARM::t2LDRSHi12: in immediateOffsetOpcode()
505 case ARM::t2LDRSBi12: in immediateOffsetOpcode()
506 case ARM::t2STRi12: in immediateOffsetOpcode()
507 case ARM::t2STRBi12: in immediateOffsetOpcode()
508 case ARM::t2STRHi12: in immediateOffsetOpcode()
509 case ARM::t2PLDi12: in immediateOffsetOpcode()
510 case ARM::t2PLDWi12: in immediateOffsetOpcode()
511 case ARM::t2PLIi12: in immediateOffsetOpcode()
512 case ARM::t2LDRi8: in immediateOffsetOpcode()
513 case ARM::t2LDRHi8: in immediateOffsetOpcode()
514 case ARM::t2LDRBi8: in immediateOffsetOpcode()
515 case ARM::t2LDRSHi8: in immediateOffsetOpcode()
516 case ARM::t2LDRSBi8: in immediateOffsetOpcode()
517 case ARM::t2STRi8: in immediateOffsetOpcode()
518 case ARM::t2STRBi8: in immediateOffsetOpcode()
519 case ARM::t2STRHi8: in immediateOffsetOpcode()
520 case ARM::t2PLDi8: in immediateOffsetOpcode()
521 case ARM::t2PLDWi8: in immediateOffsetOpcode()
522 case ARM::t2PLIi8: in immediateOffsetOpcode()
544 if (Opcode == ARM::INLINEASM || Opcode == ARM::INLINEASM_BR) in rewriteT2FrameIndex()
547 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm; in rewriteT2FrameIndex()
548 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()
553 !MI.definesRegister(ARM::CPSR)) { in rewriteT2FrameIndex()
555 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
565 bool HasCCOut = (Opcode != ARM::t2ADDspImm12 && Opcode != ARM::t2ADDri12); in rewriteT2FrameIndex()
570 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
572 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
588 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()
589 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
769 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()
781 if (ARM::isVpred(MCID.OpInfo[i].OperandType)) in findFirstVPTPredOperandIdx()
820 ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T; in recomputeVPTBlockMask()