Lines Matching refs:ARM
184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
219 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
222 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
293 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
295 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
320 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
322 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
324 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
384 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
392 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
414 if (!ARM::QPRRegClass.contains(Reg)) in PrintAsmOperand()
418 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1); in PrintAsmOperand()
433 if(!ARM::GPRPairRegClass.contains(Reg)) in PrintAsmOperand()
435 Reg = TRI->getSubReg(Reg, ARM::gsub_1); in PrintAsmOperand()
471 return STI.getFeatureBits()[ARM::ModeThumb]; in isThumb()
1046 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B) in emitJumpTableInsts()
1122 case ARM::tPUSH: in EmitUnwindingInstruction()
1124 SrcReg = DstReg = ARM::SP; in EmitUnwindingInstruction()
1126 case ARM::tLDRpci: in EmitUnwindingInstruction()
1127 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1128 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1146 assert(DstReg == ARM::SP && in EmitUnwindingInstruction()
1165 case ARM::tPUSH: in EmitUnwindingInstruction()
1169 case ARM::STMDB_UPD: in EmitUnwindingInstruction()
1170 case ARM::t2STMDB_UPD: in EmitUnwindingInstruction()
1171 case ARM::VSTMDDB_UPD: in EmitUnwindingInstruction()
1172 assert(SrcReg == ARM::SP && in EmitUnwindingInstruction()
1201 case ARM::STR_PRE_IMM: in EmitUnwindingInstruction()
1202 case ARM::STR_PRE_REG: in EmitUnwindingInstruction()
1203 case ARM::t2STR_PRE: in EmitUnwindingInstruction()
1204 assert(MI->getOperand(2).getReg() == ARM::SP && in EmitUnwindingInstruction()
1211 case ARM::t2STRD_PRE: in EmitUnwindingInstruction()
1212 assert(MI->getOperand(3).getReg() == ARM::SP && in EmitUnwindingInstruction()
1225 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1228 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
1235 if (SrcReg == ARM::SP) { in EmitUnwindingInstruction()
1241 case ARM::MOVr: in EmitUnwindingInstruction()
1242 case ARM::tMOVr: in EmitUnwindingInstruction()
1245 case ARM::ADDri: in EmitUnwindingInstruction()
1246 case ARM::t2ADDri: in EmitUnwindingInstruction()
1247 case ARM::t2ADDri12: in EmitUnwindingInstruction()
1248 case ARM::t2ADDspImm: in EmitUnwindingInstruction()
1249 case ARM::t2ADDspImm12: in EmitUnwindingInstruction()
1252 case ARM::SUBri: in EmitUnwindingInstruction()
1253 case ARM::t2SUBri: in EmitUnwindingInstruction()
1254 case ARM::t2SUBri12: in EmitUnwindingInstruction()
1255 case ARM::t2SUBspImm: in EmitUnwindingInstruction()
1256 case ARM::t2SUBspImm12: in EmitUnwindingInstruction()
1259 case ARM::tSUBspi: in EmitUnwindingInstruction()
1262 case ARM::tADDspi: in EmitUnwindingInstruction()
1263 case ARM::tADDrSPi: in EmitUnwindingInstruction()
1266 case ARM::tADDhirr: in EmitUnwindingInstruction()
1272 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) { in EmitUnwindingInstruction()
1273 if (DstReg == FramePtr && FramePtr != ARM::SP) in EmitUnwindingInstruction()
1276 ATS.emitSetFP(FramePtr, ARM::SP, -Offset); in EmitUnwindingInstruction()
1277 else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1287 } else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1293 case ARM::tMOVr: in EmitUnwindingInstruction()
1299 case ARM::tLDRpci: { in EmitUnwindingInstruction()
1315 case ARM::t2MOVi16: in EmitUnwindingInstruction()
1319 case ARM::t2MOVTi16: in EmitUnwindingInstruction()
1323 case ARM::t2PAC: in EmitUnwindingInstruction()
1324 case ARM::t2PACBTI: in EmitUnwindingInstruction()
1325 AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE; in EmitUnwindingInstruction()
1349 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) { in emitInstruction()
1369 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); in emitInstruction()
1370 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); in emitInstruction()
1371 case ARM::LEApcrel: in emitInstruction()
1372 case ARM::tLEApcrel: in emitInstruction()
1373 case ARM::t2LEApcrel: { in emitInstruction()
1377 ARM::t2LEApcrel ? ARM::t2ADR in emitInstruction()
1378 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR in emitInstruction()
1379 : ARM::ADR)) in emitInstruction()
1387 case ARM::LEApcrelJT: in emitInstruction()
1388 case ARM::tLEApcrelJT: in emitInstruction()
1389 case ARM::t2LEApcrelJT: { in emitInstruction()
1393 ARM::t2LEApcrelJT ? ARM::t2ADR in emitInstruction()
1394 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR in emitInstruction()
1395 : ARM::ADR)) in emitInstruction()
1405 case ARM::BX_CALL: { in emitInstruction()
1406 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1407 .addReg(ARM::LR) in emitInstruction()
1408 .addReg(ARM::PC) in emitInstruction()
1416 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
1420 case ARM::tBX_CALL: { in emitInstruction()
1445 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL) in emitInstruction()
1451 case ARM::BMOVPCRX_CALL: { in emitInstruction()
1452 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1453 .addReg(ARM::LR) in emitInstruction()
1454 .addReg(ARM::PC) in emitInstruction()
1461 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1462 .addReg(ARM::PC) in emitInstruction()
1471 case ARM::BMOVPCB_CALL: { in emitInstruction()
1472 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr) in emitInstruction()
1473 .addReg(ARM::LR) in emitInstruction()
1474 .addReg(ARM::PC) in emitInstruction()
1486 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc) in emitInstruction()
1493 case ARM::MOVi16_ga_pcrel: in emitInstruction()
1494 case ARM::t2MOVi16_ga_pcrel: { in emitInstruction()
1496 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16); in emitInstruction()
1508 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1524 case ARM::MOVTi16_ga_pcrel: in emitInstruction()
1525 case ARM::t2MOVTi16_ga_pcrel: { in emitInstruction()
1527 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel in emitInstruction()
1528 ? ARM::MOVTi16 : ARM::t2MOVTi16); in emitInstruction()
1541 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4; in emitInstruction()
1556 case ARM::t2BFi: in emitInstruction()
1557 case ARM::t2BFic: in emitInstruction()
1558 case ARM::t2BFLi: in emitInstruction()
1559 case ARM::t2BFr: in emitInstruction()
1560 case ARM::t2BFLr: { in emitInstruction()
1592 if (Opc == ARM::t2BFic) { in emitInstruction()
1607 case ARM::t2BF_LabelPseudo: { in emitInstruction()
1616 case ARM::tPICADD: { in emitInstruction()
1628 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1631 .addReg(ARM::PC) in emitInstruction()
1637 case ARM::PICADD: { in emitInstruction()
1649 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1651 .addReg(ARM::PC) in emitInstruction()
1660 case ARM::PICSTR: in emitInstruction()
1661 case ARM::PICSTRB: in emitInstruction()
1662 case ARM::PICSTRH: in emitInstruction()
1663 case ARM::PICLDR: in emitInstruction()
1664 case ARM::PICLDRB: in emitInstruction()
1665 case ARM::PICLDRH: in emitInstruction()
1666 case ARM::PICLDRSB: in emitInstruction()
1667 case ARM::PICLDRSH: { in emitInstruction()
1684 case ARM::PICSTR: Opcode = ARM::STRrs; break; in emitInstruction()
1685 case ARM::PICSTRB: Opcode = ARM::STRBrs; break; in emitInstruction()
1686 case ARM::PICSTRH: Opcode = ARM::STRH; break; in emitInstruction()
1687 case ARM::PICLDR: Opcode = ARM::LDRrs; break; in emitInstruction()
1688 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break; in emitInstruction()
1689 case ARM::PICLDRH: Opcode = ARM::LDRH; break; in emitInstruction()
1690 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; in emitInstruction()
1691 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; in emitInstruction()
1695 .addReg(ARM::PC) in emitInstruction()
1704 case ARM::CONSTPOOL_ENTRY: { in emitInstruction()
1731 case ARM::JUMPTABLE_ADDRS: in emitInstruction()
1734 case ARM::JUMPTABLE_INSTS: in emitInstruction()
1737 case ARM::JUMPTABLE_TBB: in emitInstruction()
1738 case ARM::JUMPTABLE_TBH: in emitInstruction()
1739 emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); in emitInstruction()
1741 case ARM::t2BR_JT: { in emitInstruction()
1742 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
1743 .addReg(ARM::PC) in emitInstruction()
1750 case ARM::t2TBB_JT: in emitInstruction()
1751 case ARM::t2TBH_JT: { in emitInstruction()
1752 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH; in emitInstruction()
1763 case ARM::tTBB_JT: in emitInstruction()
1764 case ARM::tTBH_JT: { in emitInstruction()
1766 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT; in emitInstruction()
1773 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1775 .addReg(ARM::CPSR) in emitInstruction()
1782 if (Base == ARM::PC) { in emitInstruction()
1797 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1805 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi; in emitInstruction()
1819 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr; in emitInstruction()
1829 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) in emitInstruction()
1831 .addReg(ARM::CPSR) in emitInstruction()
1839 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) in emitInstruction()
1840 .addReg(ARM::PC) in emitInstruction()
1841 .addReg(ARM::PC) in emitInstruction()
1848 case ARM::tBR_JTr: in emitInstruction()
1849 case ARM::BR_JTr: { in emitInstruction()
1852 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ? in emitInstruction()
1853 ARM::MOVr : ARM::tMOVr; in emitInstruction()
1855 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1861 if (Opc == ARM::MOVr) in emitInstruction()
1866 case ARM::BR_JTm_i12: { in emitInstruction()
1869 TmpInst.setOpcode(ARM::LDRi12); in emitInstruction()
1870 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1879 case ARM::BR_JTm_rs: { in emitInstruction()
1882 TmpInst.setOpcode(ARM::LDRrs); in emitInstruction()
1883 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1893 case ARM::BR_JTadd: { in emitInstruction()
1895 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr) in emitInstruction()
1896 .addReg(ARM::PC) in emitInstruction()
1906 case ARM::SPACE: in emitInstruction()
1909 case ARM::TRAP: { in emitInstruction()
1920 case ARM::TRAPNaCl: { in emitInstruction()
1926 case ARM::tTRAP: { in emitInstruction()
1937 case ARM::t2Int_eh_sjlj_setjmp: in emitInstruction()
1938 case ARM::t2Int_eh_sjlj_setjmp_nofp: in emitInstruction()
1939 case ARM::tInt_eh_sjlj_setjmp: { in emitInstruction()
1952 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
1954 .addReg(ARM::PC) in emitInstruction()
1959 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3) in emitInstruction()
1962 .addReg(ARM::CPSR) in emitInstruction()
1969 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi) in emitInstruction()
1979 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
1980 .addReg(ARM::R0) in emitInstruction()
1981 .addReg(ARM::CPSR) in emitInstruction()
1988 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB) in emitInstruction()
1994 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) in emitInstruction()
1995 .addReg(ARM::R0) in emitInstruction()
1996 .addReg(ARM::CPSR) in emitInstruction()
2006 case ARM::Int_eh_sjlj_setjmp_nofp: in emitInstruction()
2007 case ARM::Int_eh_sjlj_setjmp: { in emitInstruction()
2018 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
2020 .addReg(ARM::PC) in emitInstruction()
2028 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12) in emitInstruction()
2036 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
2037 .addReg(ARM::R0) in emitInstruction()
2045 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in emitInstruction()
2046 .addReg(ARM::PC) in emitInstruction()
2047 .addReg(ARM::PC) in emitInstruction()
2056 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi) in emitInstruction()
2057 .addReg(ARM::R0) in emitInstruction()
2066 case ARM::Int_eh_sjlj_longjmp: { in emitInstruction()
2073 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2074 .addReg(ARM::SP) in emitInstruction()
2081 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2094 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2104 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2105 .addReg(ARM::R7) in emitInstruction()
2111 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) in emitInstruction()
2112 .addReg(ARM::R11) in emitInstruction()
2121 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in emitInstruction()
2128 case ARM::tInt_eh_sjlj_longjmp: { in emitInstruction()
2140 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2150 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) in emitInstruction()
2151 .addReg(ARM::SP) in emitInstruction()
2157 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2167 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2177 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2178 .addReg(ARM::R7) in emitInstruction()
2184 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) in emitInstruction()
2185 .addReg(ARM::R11) in emitInstruction()
2193 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in emitInstruction()
2200 case ARM::tInt_WIN_eh_sjlj_longjmp: { in emitInstruction()
2207 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2208 .addReg(ARM::R11) in emitInstruction()
2214 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2215 .addReg(ARM::SP) in emitInstruction()
2221 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12) in emitInstruction()
2222 .addReg(ARM::PC) in emitInstruction()
2230 case ARM::PATCHABLE_FUNCTION_ENTER: in emitInstruction()
2233 case ARM::PATCHABLE_FUNCTION_EXIT: in emitInstruction()
2236 case ARM::PATCHABLE_TAIL_CALL: in emitInstruction()
2239 case ARM::SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2242 TmpInstDSB.setOpcode(ARM::DSB); in emitInstruction()
2246 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction()
2251 case ARM::t2SpeculationBarrierISBDSBEndBB: { in emitInstruction()
2254 TmpInstDSB.setOpcode(ARM::t2DSB); in emitInstruction()
2260 TmpInstISB.setOpcode(ARM::t2ISB); in emitInstruction()
2267 case ARM::SpeculationBarrierSBEndBB: { in emitInstruction()
2270 TmpInstSB.setOpcode(ARM::SB); in emitInstruction()
2274 case ARM::t2SpeculationBarrierSBEndBB: { in emitInstruction()
2277 TmpInstSB.setOpcode(ARM::t2SB); in emitInstruction()
2282 case ARM::SEH_StackAlloc: in emitInstruction()
2287 case ARM::SEH_SaveRegs: in emitInstruction()
2288 case ARM::SEH_SaveRegs_Ret: in emitInstruction()
2293 case ARM::SEH_SaveSP: in emitInstruction()
2297 case ARM::SEH_SaveFRegs: in emitInstruction()
2302 case ARM::SEH_SaveLR: in emitInstruction()
2306 case ARM::SEH_Nop: in emitInstruction()
2307 case ARM::SEH_Nop_Ret: in emitInstruction()
2311 case ARM::SEH_PrologEnd: in emitInstruction()
2315 case ARM::SEH_EpilogStart: in emitInstruction()
2319 case ARM::SEH_EpilogEnd: in emitInstruction()