Lines Matching refs:ARM
117 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
513 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1595 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1599 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1603 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1610 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1611 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1616 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1622 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1626 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
1629 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
1635 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) { in tryARMIndexedLoad()
1681 SDNode *New = CurDAG->getMachineNode(ARM::tLDR_postidx, SDLoc(N), MVT::i32, in tryT1IndexedLoad()
1703 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1707 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; in tryT2IndexedLoad()
1709 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; in tryT2IndexedLoad()
1714 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; in tryT2IndexedLoad()
1716 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; in tryT2IndexedLoad()
1792 Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post; in tryMVEIndexedLoad()
1794 Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post; in tryMVEIndexedLoad()
1798 Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post; in tryMVEIndexedLoad()
1800 Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post; in tryMVEIndexedLoad()
1804 Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post; in tryMVEIndexedLoad()
1806 Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post; in tryMVEIndexedLoad()
1811 Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post; in tryMVEIndexedLoad()
1816 Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post; in tryMVEIndexedLoad()
1819 Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post; in tryMVEIndexedLoad()
1843 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32); in createGPRPairNode()
1844 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in createGPRPairNode()
1845 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode()
1854 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, dl, MVT::i32); in createSRegPairNode()
1855 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createSRegPairNode()
1856 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode()
1864 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode()
1866 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createDRegPairNode()
1867 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode()
1875 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode()
1877 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQRegPairNode()
1878 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode()
1888 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, dl, MVT::i32); in createQuadSRegsNode()
1889 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); in createQuadSRegsNode()
1890 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode()
1891 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, dl, MVT::i32); in createQuadSRegsNode()
1892 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, dl, MVT::i32); in createQuadSRegsNode()
1902 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode()
1904 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); in createQuadDRegsNode()
1905 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode()
1906 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, dl, MVT::i32); in createQuadDRegsNode()
1907 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, dl, MVT::i32); in createQuadDRegsNode()
1917 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode()
1919 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); in createQuadQRegsNode()
1920 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode()
1921 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, dl, MVT::i32); in createQuadQRegsNode()
1922 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, dl, MVT::i32); in createQuadQRegsNode()
1954 case ARM::VLD1d8wb_fixed : return true; in isVLDfixed()
1955 case ARM::VLD1d16wb_fixed : return true; in isVLDfixed()
1956 case ARM::VLD1d64Qwb_fixed : return true; in isVLDfixed()
1957 case ARM::VLD1d32wb_fixed : return true; in isVLDfixed()
1958 case ARM::VLD1d64wb_fixed : return true; in isVLDfixed()
1959 case ARM::VLD1d8TPseudoWB_fixed : return true; in isVLDfixed()
1960 case ARM::VLD1d16TPseudoWB_fixed : return true; in isVLDfixed()
1961 case ARM::VLD1d32TPseudoWB_fixed : return true; in isVLDfixed()
1962 case ARM::VLD1d64TPseudoWB_fixed : return true; in isVLDfixed()
1963 case ARM::VLD1d8QPseudoWB_fixed : return true; in isVLDfixed()
1964 case ARM::VLD1d16QPseudoWB_fixed : return true; in isVLDfixed()
1965 case ARM::VLD1d32QPseudoWB_fixed : return true; in isVLDfixed()
1966 case ARM::VLD1d64QPseudoWB_fixed : return true; in isVLDfixed()
1967 case ARM::VLD1q8wb_fixed : return true; in isVLDfixed()
1968 case ARM::VLD1q16wb_fixed : return true; in isVLDfixed()
1969 case ARM::VLD1q32wb_fixed : return true; in isVLDfixed()
1970 case ARM::VLD1q64wb_fixed : return true; in isVLDfixed()
1971 case ARM::VLD1DUPd8wb_fixed : return true; in isVLDfixed()
1972 case ARM::VLD1DUPd16wb_fixed : return true; in isVLDfixed()
1973 case ARM::VLD1DUPd32wb_fixed : return true; in isVLDfixed()
1974 case ARM::VLD1DUPq8wb_fixed : return true; in isVLDfixed()
1975 case ARM::VLD1DUPq16wb_fixed : return true; in isVLDfixed()
1976 case ARM::VLD1DUPq32wb_fixed : return true; in isVLDfixed()
1977 case ARM::VLD2d8wb_fixed : return true; in isVLDfixed()
1978 case ARM::VLD2d16wb_fixed : return true; in isVLDfixed()
1979 case ARM::VLD2d32wb_fixed : return true; in isVLDfixed()
1980 case ARM::VLD2q8PseudoWB_fixed : return true; in isVLDfixed()
1981 case ARM::VLD2q16PseudoWB_fixed : return true; in isVLDfixed()
1982 case ARM::VLD2q32PseudoWB_fixed : return true; in isVLDfixed()
1983 case ARM::VLD2DUPd8wb_fixed : return true; in isVLDfixed()
1984 case ARM::VLD2DUPd16wb_fixed : return true; in isVLDfixed()
1985 case ARM::VLD2DUPd32wb_fixed : return true; in isVLDfixed()
1986 case ARM::VLD2DUPq8OddPseudoWB_fixed: return true; in isVLDfixed()
1987 case ARM::VLD2DUPq16OddPseudoWB_fixed: return true; in isVLDfixed()
1988 case ARM::VLD2DUPq32OddPseudoWB_fixed: return true; in isVLDfixed()
1996 case ARM::VST1d8wb_fixed : return true; in isVSTfixed()
1997 case ARM::VST1d16wb_fixed : return true; in isVSTfixed()
1998 case ARM::VST1d32wb_fixed : return true; in isVSTfixed()
1999 case ARM::VST1d64wb_fixed : return true; in isVSTfixed()
2000 case ARM::VST1q8wb_fixed : return true; in isVSTfixed()
2001 case ARM::VST1q16wb_fixed : return true; in isVSTfixed()
2002 case ARM::VST1q32wb_fixed : return true; in isVSTfixed()
2003 case ARM::VST1q64wb_fixed : return true; in isVSTfixed()
2004 case ARM::VST1d8TPseudoWB_fixed : return true; in isVSTfixed()
2005 case ARM::VST1d16TPseudoWB_fixed : return true; in isVSTfixed()
2006 case ARM::VST1d32TPseudoWB_fixed : return true; in isVSTfixed()
2007 case ARM::VST1d64TPseudoWB_fixed : return true; in isVSTfixed()
2008 case ARM::VST1d8QPseudoWB_fixed : return true; in isVSTfixed()
2009 case ARM::VST1d16QPseudoWB_fixed : return true; in isVSTfixed()
2010 case ARM::VST1d32QPseudoWB_fixed : return true; in isVSTfixed()
2011 case ARM::VST1d64QPseudoWB_fixed : return true; in isVSTfixed()
2012 case ARM::VST2d8wb_fixed : return true; in isVSTfixed()
2013 case ARM::VST2d16wb_fixed : return true; in isVSTfixed()
2014 case ARM::VST2d32wb_fixed : return true; in isVSTfixed()
2015 case ARM::VST2q8PseudoWB_fixed : return true; in isVSTfixed()
2016 case ARM::VST2q16PseudoWB_fixed : return true; in isVSTfixed()
2017 case ARM::VST2q32PseudoWB_fixed : return true; in isVSTfixed()
2028 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2029 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2030 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2031 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2032 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2033 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2034 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2035 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2036 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register; in getVLDSTRegisterUpdateOpcode()
2037 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register; in getVLDSTRegisterUpdateOpcode()
2038 case ARM::VLD1d8TPseudoWB_fixed: return ARM::VLD1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2039 case ARM::VLD1d16TPseudoWB_fixed: return ARM::VLD1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2040 case ARM::VLD1d32TPseudoWB_fixed: return ARM::VLD1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2041 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2042 case ARM::VLD1d8QPseudoWB_fixed: return ARM::VLD1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2043 case ARM::VLD1d16QPseudoWB_fixed: return ARM::VLD1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2044 case ARM::VLD1d32QPseudoWB_fixed: return ARM::VLD1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2045 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2046 case ARM::VLD1DUPd8wb_fixed : return ARM::VLD1DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2047 case ARM::VLD1DUPd16wb_fixed : return ARM::VLD1DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2048 case ARM::VLD1DUPd32wb_fixed : return ARM::VLD1DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2049 case ARM::VLD1DUPq8wb_fixed : return ARM::VLD1DUPq8wb_register; in getVLDSTRegisterUpdateOpcode()
2050 case ARM::VLD1DUPq16wb_fixed : return ARM::VLD1DUPq16wb_register; in getVLDSTRegisterUpdateOpcode()
2051 case ARM::VLD1DUPq32wb_fixed : return ARM::VLD1DUPq32wb_register; in getVLDSTRegisterUpdateOpcode()
2052 case ARM::VLD2DUPq8OddPseudoWB_fixed: return ARM::VLD2DUPq8OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2053 case ARM::VLD2DUPq16OddPseudoWB_fixed: return ARM::VLD2DUPq16OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2054 case ARM::VLD2DUPq32OddPseudoWB_fixed: return ARM::VLD2DUPq32OddPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2056 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register; in getVLDSTRegisterUpdateOpcode()
2057 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register; in getVLDSTRegisterUpdateOpcode()
2058 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register; in getVLDSTRegisterUpdateOpcode()
2059 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register; in getVLDSTRegisterUpdateOpcode()
2060 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register; in getVLDSTRegisterUpdateOpcode()
2061 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register; in getVLDSTRegisterUpdateOpcode()
2062 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register; in getVLDSTRegisterUpdateOpcode()
2063 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register; in getVLDSTRegisterUpdateOpcode()
2064 case ARM::VST1d8TPseudoWB_fixed: return ARM::VST1d8TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2065 case ARM::VST1d16TPseudoWB_fixed: return ARM::VST1d16TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2066 case ARM::VST1d32TPseudoWB_fixed: return ARM::VST1d32TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2067 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2068 case ARM::VST1d8QPseudoWB_fixed: return ARM::VST1d8QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2069 case ARM::VST1d16QPseudoWB_fixed: return ARM::VST1d16QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2070 case ARM::VST1d32QPseudoWB_fixed: return ARM::VST1d32QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2071 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2073 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2074 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2075 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2076 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2077 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2078 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2080 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register; in getVLDSTRegisterUpdateOpcode()
2081 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register; in getVLDSTRegisterUpdateOpcode()
2082 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register; in getVLDSTRegisterUpdateOpcode()
2083 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2084 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2085 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register; in getVLDSTRegisterUpdateOpcode()
2087 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register; in getVLDSTRegisterUpdateOpcode()
2088 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register; in getVLDSTRegisterUpdateOpcode()
2089 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register; in getVLDSTRegisterUpdateOpcode()
2231 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLD()
2232 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLD()
2234 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2515 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7 && in SelectVLDSTLane()
2516 ARM::qsub_3 == ARM::qsub_0 + 3, in SelectVLDSTLane()
2518 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()
2688 CurDAG->SelectNodeTo(N, ARM::MVE_VSHLC, N->getVTList(), makeArrayRef(Ops)); in SelectMVE_VSHLC()
2830 CurDAG->getTargetExtractSubreg(ARM::qsub_0 + i, Loc, VT, in SelectMVE_VLD()
2929 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD()
3062 static_assert(ARM::dsub_7 == ARM::dsub_0 + 7, "Unexpected subreg numbering"); in SelectVLDDup()
3063 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDDup()
3124 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3126 ARM::ssub_0 + Lane2 / 2, dl, VT, Ins2.getOperand(0), in tryInsertVectorElt()
3136 ARM::ssub_0 + ExtractLane1 / 2, dl, MVT::f32, Val1.getOperand(0)); in tryInsertVectorElt()
3138 ARM::ssub_0 + ExtractLane2 / 2, dl, MVT::f32, Val2.getOperand(0)); in tryInsertVectorElt()
3140 Inp1 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp1), 0); in tryInsertVectorElt()
3142 Inp2 = SDValue(CurDAG->getMachineNode(ARM::VMOVH, dl, MVT::f32, Inp2), 0); in tryInsertVectorElt()
3143 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Inp2, Inp1); in tryInsertVectorElt()
3145 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3155 SDNode *VINS = CurDAG->getMachineNode(ARM::VINSH, dl, MVT::f32, Val2, Val1); in tryInsertVectorElt()
3157 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3249 Opcode = IsUnsigned ? ARM::MVE_VCVTf16u16_fix : ARM::MVE_VCVTf16s16_fix; in transformFixedFloatingPointConversion()
3251 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in transformFixedFloatingPointConversion()
3255 Opcode = IsUnsigned ? ARM::MVE_VCVTf32u32_fix : ARM::MVE_VCVTf32s32_fix; in transformFixedFloatingPointConversion()
3257 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in transformFixedFloatingPointConversion()
3295 Opcode = IsUnsigned ? ARM::MVE_VCVTu16f16_fix : ARM::MVE_VCVTs16f16_fix; in tryFP_TO_INT()
3298 Opcode = IsUnsigned ? ARM::MVE_VCVTu32f32_fix : ARM::MVE_VCVTs32f32_fix; in tryFP_TO_INT()
3336 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX) in tryV6T2BitfieldExtractOp()
3337 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX); in tryV6T2BitfieldExtractOp()
3368 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri; in tryV6T2BitfieldExtractOp()
3383 CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops); in tryV6T2BitfieldExtractOp()
3498 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; in tryABSOp()
3511 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_8 : ARM::CMP_SWAP_8; in SelectCMP_SWAP()
3513 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_16 : ARM::CMP_SWAP_16; in SelectCMP_SWAP()
3515 Opcode = Subtarget->isThumb() ? ARM::tCMP_SWAP_32 : ARM::CMP_SWAP_32; in SelectCMP_SWAP()
3575 Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri; in SelectCMPZ()
3581 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ()
3590 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3594 NewN = EmitShift(ARM::tLSRri, X, Range->second); in SelectCMPZ()
3599 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3606 NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first); in SelectCMPZ()
3607 NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0), in SelectCMPZ()
3644 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP && in Select()
3647 CurDAG->getRegister(ARM::SP, MVT::i32), in Select()
3653 CurDAG->getMachineNode(ARM::tSTRspi, dl, MVT::Other, Ops); in Select()
3697 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, in Select()
3707 ResNode = CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, in Select()
3738 CurDAG->SelectNodeTo(N, ARM::tADDframe, MVT::i32, TFI, in Select()
3743 ARM::t2ADDri : ARM::ADDri); in Select()
3792 CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops); in Select()
3797 CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops); in Select()
3811 CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops); in Select()
3816 CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops); in Select()
3853 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select()
3856 ReplaceNode(N, CurDAG->getMachineNode(ARM::tBIC, dl, MVT::i32, Ops)); in Select()
3863 CurDAG->getMachineNode(ARM::t2BICrr, dl, MVT::i32, Ops)); in Select()
3878 ? ARM::t2MOVTi16 in Select()
3879 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0); in Select()
3908 unsigned Opc = Subtarget->isThumb() ? ARM::t2UMAAL : ARM::UMAAL; in Select()
3922 N, CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3930 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
3941 N, CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops)); in Select()
3949 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
3978 unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS; in Select()
4005 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopSetup, dl, MVT::i32, in Select()
4012 SDNode *New = CurDAG->getMachineNode(ARM::t2WhileLoopStart, dl, MVT::Other, in Select()
4023 unsigned Opc = ARM::t2LoopEnd; in Select()
4045 SDNode *New = CurDAG->getMachineNode(ARM::LOADDUAL, dl, in Select()
4047 SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in Select()
4049 SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in Select()
4076 SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops); in Select()
4087 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4107 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc; in Select()
4133 CurDAG->getMachineNode(ARM::t2LoopDec, dl, in Select()
4140 CurDAG->getMachineNode(ARM::t2LoopEnd, dl, MVT::Other, EndArgs); in Select()
4202 Add = CurDAG->getMachineNode(ARM::t2ADDri, dl, MVT::i32, Ops); in Select()
4204 unsigned Opc = (Addend < 1<<3) ? ARM::tADDi3 : ARM::tADDi8; in Select()
4205 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select()
4257 case MVT::v8i8: Opc = ARM::VZIPd8; break; in Select()
4259 case MVT::v4i16: Opc = ARM::VZIPd16; break; in Select()
4262 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4263 case MVT::v16i8: Opc = ARM::VZIPq8; break; in Select()
4265 case MVT::v8i16: Opc = ARM::VZIPq16; break; in Select()
4267 case MVT::v4i32: Opc = ARM::VZIPq32; break; in Select()
4280 case MVT::v8i8: Opc = ARM::VUZPd8; break; in Select()
4282 case MVT::v4i16: Opc = ARM::VUZPd16; break; in Select()
4285 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4286 case MVT::v16i8: Opc = ARM::VUZPq8; break; in Select()
4288 case MVT::v8i16: Opc = ARM::VUZPq16; break; in Select()
4290 case MVT::v4i32: Opc = ARM::VUZPq32; break; in Select()
4303 case MVT::v8i8: Opc = ARM::VTRNd8; break; in Select()
4305 case MVT::v4i16: Opc = ARM::VTRNd16; break; in Select()
4307 case MVT::v2i32: Opc = ARM::VTRNd32; break; in Select()
4308 case MVT::v16i8: Opc = ARM::VTRNq8; break; in Select()
4310 case MVT::v8i16: Opc = ARM::VTRNq16; break; in Select()
4312 case MVT::v4i32: Opc = ARM::VTRNq32; break; in Select()
4344 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8, ARM::VLD1DUPd16, in Select()
4345 ARM::VLD1DUPd32 }; in Select()
4346 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8, ARM::VLD1DUPq16, in Select()
4347 ARM::VLD1DUPq32 }; in Select()
4353 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4354 ARM::VLD2DUPd32 }; in Select()
4360 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4361 ARM::VLD3DUPd16Pseudo, in Select()
4362 ARM::VLD3DUPd32Pseudo }; in Select()
4368 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4369 ARM::VLD4DUPd16Pseudo, in Select()
4370 ARM::VLD4DUPd32Pseudo }; in Select()
4376 static const uint16_t DOpcodes[] = { ARM::VLD1DUPd8wb_fixed, in Select()
4377 ARM::VLD1DUPd16wb_fixed, in Select()
4378 ARM::VLD1DUPd32wb_fixed }; in Select()
4379 static const uint16_t QOpcodes[] = { ARM::VLD1DUPq8wb_fixed, in Select()
4380 ARM::VLD1DUPq16wb_fixed, in Select()
4381 ARM::VLD1DUPq32wb_fixed }; in Select()
4387 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8wb_fixed, in Select()
4388 ARM::VLD2DUPd16wb_fixed, in Select()
4389 ARM::VLD2DUPd32wb_fixed, in Select()
4390 ARM::VLD1q64wb_fixed }; in Select()
4391 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4392 ARM::VLD2DUPq16EvenPseudo, in Select()
4393 ARM::VLD2DUPq32EvenPseudo }; in Select()
4394 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudoWB_fixed, in Select()
4395 ARM::VLD2DUPq16OddPseudoWB_fixed, in Select()
4396 ARM::VLD2DUPq32OddPseudoWB_fixed }; in Select()
4402 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, in Select()
4403 ARM::VLD3DUPd16Pseudo_UPD, in Select()
4404 ARM::VLD3DUPd32Pseudo_UPD, in Select()
4405 ARM::VLD1d64TPseudoWB_fixed }; in Select()
4406 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4407 ARM::VLD3DUPq16EvenPseudo, in Select()
4408 ARM::VLD3DUPq32EvenPseudo }; in Select()
4409 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo_UPD, in Select()
4410 ARM::VLD3DUPq16OddPseudo_UPD, in Select()
4411 ARM::VLD3DUPq32OddPseudo_UPD }; in Select()
4417 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, in Select()
4418 ARM::VLD4DUPd16Pseudo_UPD, in Select()
4419 ARM::VLD4DUPd32Pseudo_UPD, in Select()
4420 ARM::VLD1d64QPseudoWB_fixed }; in Select()
4421 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4422 ARM::VLD4DUPq16EvenPseudo, in Select()
4423 ARM::VLD4DUPq32EvenPseudo }; in Select()
4424 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo_UPD, in Select()
4425 ARM::VLD4DUPq16OddPseudo_UPD, in Select()
4426 ARM::VLD4DUPq32OddPseudo_UPD }; in Select()
4432 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed, in Select()
4433 ARM::VLD1d16wb_fixed, in Select()
4434 ARM::VLD1d32wb_fixed, in Select()
4435 ARM::VLD1d64wb_fixed }; in Select()
4436 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed, in Select()
4437 ARM::VLD1q16wb_fixed, in Select()
4438 ARM::VLD1q32wb_fixed, in Select()
4439 ARM::VLD1q64wb_fixed }; in Select()
4447 ARM::VLD2d8wb_fixed, ARM::VLD2d16wb_fixed, ARM::VLD2d32wb_fixed, in Select()
4448 ARM::VLD1q64wb_fixed}; in Select()
4449 static const uint16_t QOpcodes[] = {ARM::VLD2q8PseudoWB_fixed, in Select()
4450 ARM::VLD2q16PseudoWB_fixed, in Select()
4451 ARM::VLD2q32PseudoWB_fixed}; in Select()
4454 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, in Select()
4455 ARM::MVE_VLD21_8_wb}; in Select()
4456 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
4457 ARM::MVE_VLD21_16_wb}; in Select()
4458 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
4459 ARM::MVE_VLD21_32_wb}; in Select()
4467 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, in Select()
4468 ARM::VLD3d16Pseudo_UPD, in Select()
4469 ARM::VLD3d32Pseudo_UPD, in Select()
4470 ARM::VLD1d64TPseudoWB_fixed}; in Select()
4471 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4472 ARM::VLD3q16Pseudo_UPD, in Select()
4473 ARM::VLD3q32Pseudo_UPD }; in Select()
4474 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, in Select()
4475 ARM::VLD3q16oddPseudo_UPD, in Select()
4476 ARM::VLD3q32oddPseudo_UPD }; in Select()
4484 ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD, ARM::VLD4d32Pseudo_UPD, in Select()
4485 ARM::VLD1d64QPseudoWB_fixed}; in Select()
4486 static const uint16_t QOpcodes0[] = {ARM::VLD4q8Pseudo_UPD, in Select()
4487 ARM::VLD4q16Pseudo_UPD, in Select()
4488 ARM::VLD4q32Pseudo_UPD}; in Select()
4489 static const uint16_t QOpcodes1[] = {ARM::VLD4q8oddPseudo_UPD, in Select()
4490 ARM::VLD4q16oddPseudo_UPD, in Select()
4491 ARM::VLD4q32oddPseudo_UPD}; in Select()
4494 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
4495 ARM::MVE_VLD42_8, in Select()
4496 ARM::MVE_VLD43_8_wb}; in Select()
4497 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
4498 ARM::MVE_VLD42_16, in Select()
4499 ARM::MVE_VLD43_16_wb}; in Select()
4500 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
4501 ARM::MVE_VLD42_32, in Select()
4502 ARM::MVE_VLD43_32_wb}; in Select()
4512 ARM::VLD1q8wb_fixed, ARM::VLD1q16wb_fixed, ARM::VLD1q32wb_fixed, in Select()
4513 ARM::VLD1q64wb_fixed}; in Select()
4515 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4516 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4526 ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d16TPseudoWB_fixed, in Select()
4527 ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d64TPseudoWB_fixed}; in Select()
4529 ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1q16LowTPseudo_UPD, in Select()
4530 ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1q64LowTPseudo_UPD}; in Select()
4532 ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1q16HighTPseudo_UPD, in Select()
4533 ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1q64HighTPseudo_UPD}; in Select()
4543 ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d16QPseudoWB_fixed, in Select()
4544 ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d64QPseudoWB_fixed}; in Select()
4546 ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1q16LowQPseudo_UPD, in Select()
4547 ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1q64LowQPseudo_UPD}; in Select()
4549 ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1q16HighQPseudo_UPD, in Select()
4550 ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1q64HighQPseudo_UPD}; in Select()
4558 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, in Select()
4559 ARM::VLD2LNd16Pseudo_UPD, in Select()
4560 ARM::VLD2LNd32Pseudo_UPD }; in Select()
4561 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD, in Select()
4562 ARM::VLD2LNq32Pseudo_UPD }; in Select()
4568 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, in Select()
4569 ARM::VLD3LNd16Pseudo_UPD, in Select()
4570 ARM::VLD3LNd32Pseudo_UPD }; in Select()
4571 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD, in Select()
4572 ARM::VLD3LNq32Pseudo_UPD }; in Select()
4578 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, in Select()
4579 ARM::VLD4LNd16Pseudo_UPD, in Select()
4580 ARM::VLD4LNd32Pseudo_UPD }; in Select()
4581 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD, in Select()
4582 ARM::VLD4LNq32Pseudo_UPD }; in Select()
4588 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed, in Select()
4589 ARM::VST1d16wb_fixed, in Select()
4590 ARM::VST1d32wb_fixed, in Select()
4591 ARM::VST1d64wb_fixed }; in Select()
4592 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4593 ARM::VST1q16wb_fixed, in Select()
4594 ARM::VST1q32wb_fixed, in Select()
4595 ARM::VST1q64wb_fixed }; in Select()
4603 ARM::VST2d8wb_fixed, ARM::VST2d16wb_fixed, ARM::VST2d32wb_fixed, in Select()
4604 ARM::VST1q64wb_fixed}; in Select()
4605 static const uint16_t QOpcodes[] = {ARM::VST2q8PseudoWB_fixed, in Select()
4606 ARM::VST2q16PseudoWB_fixed, in Select()
4607 ARM::VST2q32PseudoWB_fixed}; in Select()
4615 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD, in Select()
4616 ARM::VST3d16Pseudo_UPD, in Select()
4617 ARM::VST3d32Pseudo_UPD, in Select()
4618 ARM::VST1d64TPseudoWB_fixed}; in Select()
4619 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
4620 ARM::VST3q16Pseudo_UPD, in Select()
4621 ARM::VST3q32Pseudo_UPD }; in Select()
4622 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD, in Select()
4623 ARM::VST3q16oddPseudo_UPD, in Select()
4624 ARM::VST3q32oddPseudo_UPD }; in Select()
4632 ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD, ARM::VST4d32Pseudo_UPD, in Select()
4633 ARM::VST1d64QPseudoWB_fixed}; in Select()
4634 static const uint16_t QOpcodes0[] = {ARM::VST4q8Pseudo_UPD, in Select()
4635 ARM::VST4q16Pseudo_UPD, in Select()
4636 ARM::VST4q32Pseudo_UPD}; in Select()
4637 static const uint16_t QOpcodes1[] = {ARM::VST4q8oddPseudo_UPD, in Select()
4638 ARM::VST4q16oddPseudo_UPD, in Select()
4639 ARM::VST4q32oddPseudo_UPD}; in Select()
4648 static const uint16_t DOpcodes[] = { ARM::VST1q8wb_fixed, in Select()
4649 ARM::VST1q16wb_fixed, in Select()
4650 ARM::VST1q32wb_fixed, in Select()
4651 ARM::VST1q64wb_fixed}; in Select()
4652 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4653 ARM::VST1d16QPseudoWB_fixed, in Select()
4654 ARM::VST1d32QPseudoWB_fixed, in Select()
4655 ARM::VST1d64QPseudoWB_fixed }; in Select()
4664 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudoWB_fixed, in Select()
4665 ARM::VST1d16TPseudoWB_fixed, in Select()
4666 ARM::VST1d32TPseudoWB_fixed, in Select()
4667 ARM::VST1d64TPseudoWB_fixed }; in Select()
4668 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
4669 ARM::VST1q16LowTPseudo_UPD, in Select()
4670 ARM::VST1q32LowTPseudo_UPD, in Select()
4671 ARM::VST1q64LowTPseudo_UPD }; in Select()
4672 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo_UPD, in Select()
4673 ARM::VST1q16HighTPseudo_UPD, in Select()
4674 ARM::VST1q32HighTPseudo_UPD, in Select()
4675 ARM::VST1q64HighTPseudo_UPD }; in Select()
4684 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudoWB_fixed, in Select()
4685 ARM::VST1d16QPseudoWB_fixed, in Select()
4686 ARM::VST1d32QPseudoWB_fixed, in Select()
4687 ARM::VST1d64QPseudoWB_fixed }; in Select()
4688 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
4689 ARM::VST1q16LowQPseudo_UPD, in Select()
4690 ARM::VST1q32LowQPseudo_UPD, in Select()
4691 ARM::VST1q64LowQPseudo_UPD }; in Select()
4692 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo_UPD, in Select()
4693 ARM::VST1q16HighQPseudo_UPD, in Select()
4694 ARM::VST1q32HighQPseudo_UPD, in Select()
4695 ARM::VST1q64HighQPseudo_UPD }; in Select()
4702 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, in Select()
4703 ARM::VST2LNd16Pseudo_UPD, in Select()
4704 ARM::VST2LNd32Pseudo_UPD }; in Select()
4705 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD, in Select()
4706 ARM::VST2LNq32Pseudo_UPD }; in Select()
4712 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, in Select()
4713 ARM::VST3LNd16Pseudo_UPD, in Select()
4714 ARM::VST3LNd32Pseudo_UPD }; in Select()
4715 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD, in Select()
4716 ARM::VST3LNq32Pseudo_UPD }; in Select()
4722 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, in Select()
4723 ARM::VST4LNd16Pseudo_UPD, in Select()
4724 ARM::VST4LNd32Pseudo_UPD }; in Select()
4725 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD, in Select()
4726 ARM::VST4LNq32Pseudo_UPD }; in Select()
4745 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2); in Select()
4747 Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2); in Select()
4757 if (Opc != ARM::MRRC2) { in Select()
4778 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD) in Select()
4779 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD); in Select()
4806 CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); in Select()
4819 CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in Select()
4857 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD) in Select()
4858 : (IsRelease ? ARM::STLEXD : ARM::STREXD); in Select()
4870 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, in Select()
4871 ARM::VLD1d32, ARM::VLD1d64 }; in Select()
4872 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4873 ARM::VLD1q32, ARM::VLD1q64}; in Select()
4879 static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, in Select()
4880 ARM::VLD1q32, ARM::VLD1q64 }; in Select()
4881 static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4882 ARM::VLD1d16QPseudo, in Select()
4883 ARM::VLD1d32QPseudo, in Select()
4884 ARM::VLD1d64QPseudo }; in Select()
4890 static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo, in Select()
4891 ARM::VLD1d16TPseudo, in Select()
4892 ARM::VLD1d32TPseudo, in Select()
4893 ARM::VLD1d64TPseudo }; in Select()
4894 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD, in Select()
4895 ARM::VLD1q16LowTPseudo_UPD, in Select()
4896 ARM::VLD1q32LowTPseudo_UPD, in Select()
4897 ARM::VLD1q64LowTPseudo_UPD }; in Select()
4898 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo, in Select()
4899 ARM::VLD1q16HighTPseudo, in Select()
4900 ARM::VLD1q32HighTPseudo, in Select()
4901 ARM::VLD1q64HighTPseudo }; in Select()
4907 static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo, in Select()
4908 ARM::VLD1d16QPseudo, in Select()
4909 ARM::VLD1d32QPseudo, in Select()
4910 ARM::VLD1d64QPseudo }; in Select()
4911 static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD, in Select()
4912 ARM::VLD1q16LowQPseudo_UPD, in Select()
4913 ARM::VLD1q32LowQPseudo_UPD, in Select()
4914 ARM::VLD1q64LowQPseudo_UPD }; in Select()
4915 static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo, in Select()
4916 ARM::VLD1q16HighQPseudo, in Select()
4917 ARM::VLD1q32HighQPseudo, in Select()
4918 ARM::VLD1q64HighQPseudo }; in Select()
4924 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, in Select()
4925 ARM::VLD2d32, ARM::VLD1q64 }; in Select()
4926 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, in Select()
4927 ARM::VLD2q32Pseudo }; in Select()
4933 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo, in Select()
4934 ARM::VLD3d16Pseudo, in Select()
4935 ARM::VLD3d32Pseudo, in Select()
4936 ARM::VLD1d64TPseudo }; in Select()
4937 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, in Select()
4938 ARM::VLD3q16Pseudo_UPD, in Select()
4939 ARM::VLD3q32Pseudo_UPD }; in Select()
4940 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo, in Select()
4941 ARM::VLD3q16oddPseudo, in Select()
4942 ARM::VLD3q32oddPseudo }; in Select()
4948 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo, in Select()
4949 ARM::VLD4d16Pseudo, in Select()
4950 ARM::VLD4d32Pseudo, in Select()
4951 ARM::VLD1d64QPseudo }; in Select()
4952 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, in Select()
4953 ARM::VLD4q16Pseudo_UPD, in Select()
4954 ARM::VLD4q32Pseudo_UPD }; in Select()
4955 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo, in Select()
4956 ARM::VLD4q16oddPseudo, in Select()
4957 ARM::VLD4q32oddPseudo }; in Select()
4963 static const uint16_t DOpcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16, in Select()
4964 ARM::VLD2DUPd32, ARM::VLD1q64 }; in Select()
4965 static const uint16_t QOpcodes0[] = { ARM::VLD2DUPq8EvenPseudo, in Select()
4966 ARM::VLD2DUPq16EvenPseudo, in Select()
4967 ARM::VLD2DUPq32EvenPseudo }; in Select()
4968 static const uint16_t QOpcodes1[] = { ARM::VLD2DUPq8OddPseudo, in Select()
4969 ARM::VLD2DUPq16OddPseudo, in Select()
4970 ARM::VLD2DUPq32OddPseudo }; in Select()
4977 static const uint16_t DOpcodes[] = { ARM::VLD3DUPd8Pseudo, in Select()
4978 ARM::VLD3DUPd16Pseudo, in Select()
4979 ARM::VLD3DUPd32Pseudo, in Select()
4980 ARM::VLD1d64TPseudo }; in Select()
4981 static const uint16_t QOpcodes0[] = { ARM::VLD3DUPq8EvenPseudo, in Select()
4982 ARM::VLD3DUPq16EvenPseudo, in Select()
4983 ARM::VLD3DUPq32EvenPseudo }; in Select()
4984 static const uint16_t QOpcodes1[] = { ARM::VLD3DUPq8OddPseudo, in Select()
4985 ARM::VLD3DUPq16OddPseudo, in Select()
4986 ARM::VLD3DUPq32OddPseudo }; in Select()
4993 static const uint16_t DOpcodes[] = { ARM::VLD4DUPd8Pseudo, in Select()
4994 ARM::VLD4DUPd16Pseudo, in Select()
4995 ARM::VLD4DUPd32Pseudo, in Select()
4996 ARM::VLD1d64QPseudo }; in Select()
4997 static const uint16_t QOpcodes0[] = { ARM::VLD4DUPq8EvenPseudo, in Select()
4998 ARM::VLD4DUPq16EvenPseudo, in Select()
4999 ARM::VLD4DUPq32EvenPseudo }; in Select()
5000 static const uint16_t QOpcodes1[] = { ARM::VLD4DUPq8OddPseudo, in Select()
5001 ARM::VLD4DUPq16OddPseudo, in Select()
5002 ARM::VLD4DUPq32OddPseudo }; in Select()
5009 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo, in Select()
5010 ARM::VLD2LNd16Pseudo, in Select()
5011 ARM::VLD2LNd32Pseudo }; in Select()
5012 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo, in Select()
5013 ARM::VLD2LNq32Pseudo }; in Select()
5019 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo, in Select()
5020 ARM::VLD3LNd16Pseudo, in Select()
5021 ARM::VLD3LNd32Pseudo }; in Select()
5022 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo, in Select()
5023 ARM::VLD3LNq32Pseudo }; in Select()
5029 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo, in Select()
5030 ARM::VLD4LNd16Pseudo, in Select()
5031 ARM::VLD4LNd32Pseudo }; in Select()
5032 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo, in Select()
5033 ARM::VLD4LNq32Pseudo }; in Select()
5039 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16, in Select()
5040 ARM::VST1d32, ARM::VST1d64 }; in Select()
5041 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5042 ARM::VST1q32, ARM::VST1q64 }; in Select()
5048 static const uint16_t DOpcodes[] = { ARM::VST1q8, ARM::VST1q16, in Select()
5049 ARM::VST1q32, ARM::VST1q64 }; in Select()
5050 static const uint16_t QOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5051 ARM::VST1d16QPseudo, in Select()
5052 ARM::VST1d32QPseudo, in Select()
5053 ARM::VST1d64QPseudo }; in Select()
5059 static const uint16_t DOpcodes[] = { ARM::VST1d8TPseudo, in Select()
5060 ARM::VST1d16TPseudo, in Select()
5061 ARM::VST1d32TPseudo, in Select()
5062 ARM::VST1d64TPseudo }; in Select()
5063 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowTPseudo_UPD, in Select()
5064 ARM::VST1q16LowTPseudo_UPD, in Select()
5065 ARM::VST1q32LowTPseudo_UPD, in Select()
5066 ARM::VST1q64LowTPseudo_UPD }; in Select()
5067 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighTPseudo, in Select()
5068 ARM::VST1q16HighTPseudo, in Select()
5069 ARM::VST1q32HighTPseudo, in Select()
5070 ARM::VST1q64HighTPseudo }; in Select()
5076 static const uint16_t DOpcodes[] = { ARM::VST1d8QPseudo, in Select()
5077 ARM::VST1d16QPseudo, in Select()
5078 ARM::VST1d32QPseudo, in Select()
5079 ARM::VST1d64QPseudo }; in Select()
5080 static const uint16_t QOpcodes0[] = { ARM::VST1q8LowQPseudo_UPD, in Select()
5081 ARM::VST1q16LowQPseudo_UPD, in Select()
5082 ARM::VST1q32LowQPseudo_UPD, in Select()
5083 ARM::VST1q64LowQPseudo_UPD }; in Select()
5084 static const uint16_t QOpcodes1[] = { ARM::VST1q8HighQPseudo, in Select()
5085 ARM::VST1q16HighQPseudo, in Select()
5086 ARM::VST1q32HighQPseudo, in Select()
5087 ARM::VST1q64HighQPseudo }; in Select()
5093 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16, in Select()
5094 ARM::VST2d32, ARM::VST1q64 }; in Select()
5095 static const uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo, in Select()
5096 ARM::VST2q32Pseudo }; in Select()
5102 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo, in Select()
5103 ARM::VST3d16Pseudo, in Select()
5104 ARM::VST3d32Pseudo, in Select()
5105 ARM::VST1d64TPseudo }; in Select()
5106 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD, in Select()
5107 ARM::VST3q16Pseudo_UPD, in Select()
5108 ARM::VST3q32Pseudo_UPD }; in Select()
5109 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo, in Select()
5110 ARM::VST3q16oddPseudo, in Select()
5111 ARM::VST3q32oddPseudo }; in Select()
5117 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo, in Select()
5118 ARM::VST4d16Pseudo, in Select()
5119 ARM::VST4d32Pseudo, in Select()
5120 ARM::VST1d64QPseudo }; in Select()
5121 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD, in Select()
5122 ARM::VST4q16Pseudo_UPD, in Select()
5123 ARM::VST4q32Pseudo_UPD }; in Select()
5124 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo, in Select()
5125 ARM::VST4q16oddPseudo, in Select()
5126 ARM::VST4q32oddPseudo }; in Select()
5132 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo, in Select()
5133 ARM::VST2LNd16Pseudo, in Select()
5134 ARM::VST2LNd32Pseudo }; in Select()
5135 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo, in Select()
5136 ARM::VST2LNq32Pseudo }; in Select()
5142 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo, in Select()
5143 ARM::VST3LNd16Pseudo, in Select()
5144 ARM::VST3LNd32Pseudo }; in Select()
5145 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo, in Select()
5146 ARM::VST3LNq32Pseudo }; in Select()
5152 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo, in Select()
5153 ARM::VST4LNd16Pseudo, in Select()
5154 ARM::VST4LNd32Pseudo }; in Select()
5155 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo, in Select()
5156 ARM::VST4LNq32Pseudo }; in Select()
5163 static const uint16_t Opcodes[] = {ARM::MVE_VLDRWU32_qi_pre, in Select()
5164 ARM::MVE_VLDRDU64_qi_pre}; in Select()
5171 static const uint16_t Opcodes8[] = {ARM::MVE_VLD20_8, ARM::MVE_VLD21_8}; in Select()
5172 static const uint16_t Opcodes16[] = {ARM::MVE_VLD20_16, in Select()
5173 ARM::MVE_VLD21_16}; in Select()
5174 static const uint16_t Opcodes32[] = {ARM::MVE_VLD20_32, in Select()
5175 ARM::MVE_VLD21_32}; in Select()
5182 static const uint16_t Opcodes8[] = {ARM::MVE_VLD40_8, ARM::MVE_VLD41_8, in Select()
5183 ARM::MVE_VLD42_8, ARM::MVE_VLD43_8}; in Select()
5184 static const uint16_t Opcodes16[] = {ARM::MVE_VLD40_16, ARM::MVE_VLD41_16, in Select()
5185 ARM::MVE_VLD42_16, in Select()
5186 ARM::MVE_VLD43_16}; in Select()
5187 static const uint16_t Opcodes32[] = {ARM::MVE_VLD40_32, ARM::MVE_VLD41_32, in Select()
5188 ARM::MVE_VLD42_32, in Select()
5189 ARM::MVE_VLD43_32}; in Select()
5212 CurDAG->SelectNodeTo(N, ARM::BF16_VCVTB, DestTy, Ops); in Select()
5223 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
5228 SelectMVE_LongShift(N, ARM::MVE_URSHRL, true, false); in Select()
5231 SelectMVE_LongShift(N, ARM::MVE_UQSHLL, true, false); in Select()
5234 SelectMVE_LongShift(N, ARM::MVE_SRSHRL, true, false); in Select()
5237 SelectMVE_LongShift(N, ARM::MVE_SQSHLL, true, false); in Select()
5240 SelectMVE_LongShift(N, ARM::MVE_UQRSHLL, false, true); in Select()
5243 SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true); in Select()
5248 SelectMVE_VADCSBC(N, ARM::MVE_VADC, ARM::MVE_VADCI, true, in Select()
5253 SelectMVE_VADCSBC(N, ARM::MVE_VSBC, ARM::MVE_VSBCI, true, in Select()
5264 ARM::MVE_VMLALDAVu16, ARM::MVE_VMLALDAVu32, in Select()
5265 ARM::MVE_VMLALDAVau16, ARM::MVE_VMLALDAVau32, in Select()
5268 ARM::MVE_VMLALDAVs16, ARM::MVE_VMLALDAVs32, in Select()
5269 ARM::MVE_VMLALDAVas16, ARM::MVE_VMLALDAVas32, in Select()
5270 ARM::MVE_VMLALDAVxs16, ARM::MVE_VMLALDAVxs32, in Select()
5271 ARM::MVE_VMLALDAVaxs16, ARM::MVE_VMLALDAVaxs32, in Select()
5272 ARM::MVE_VMLSLDAVs16, ARM::MVE_VMLSLDAVs32, in Select()
5273 ARM::MVE_VMLSLDAVas16, ARM::MVE_VMLSLDAVas32, in Select()
5274 ARM::MVE_VMLSLDAVxs16, ARM::MVE_VMLSLDAVxs32, in Select()
5275 ARM::MVE_VMLSLDAVaxs16, ARM::MVE_VMLSLDAVaxs32, in Select()
5285 ARM::MVE_VRMLALDAVHu32, ARM::MVE_VRMLALDAVHau32, in Select()
5288 ARM::MVE_VRMLALDAVHs32, ARM::MVE_VRMLALDAVHas32, in Select()
5289 ARM::MVE_VRMLALDAVHxs32, ARM::MVE_VRMLALDAVHaxs32, in Select()
5290 ARM::MVE_VRMLSLDAVHs32, ARM::MVE_VRMLSLDAVHas32, in Select()
5291 ARM::MVE_VRMLSLDAVHxs32, ARM::MVE_VRMLSLDAVHaxs32, in Select()
5301 ARM::MVE_VIDUPu8, ARM::MVE_VIDUPu16, ARM::MVE_VIDUPu32, in Select()
5311 ARM::MVE_VDDUPu8, ARM::MVE_VDDUPu16, ARM::MVE_VDDUPu32, in Select()
5321 ARM::MVE_VIWDUPu8, ARM::MVE_VIWDUPu16, ARM::MVE_VIWDUPu32, in Select()
5331 ARM::MVE_VDWDUPu8, ARM::MVE_VDWDUPu16, ARM::MVE_VDWDUPu32, in Select()
5353 Opcode = HasAccum ? ARM::CDE_CX1DA : ARM::CDE_CX1D; in Select()
5358 Opcode = HasAccum ? ARM::CDE_CX2DA : ARM::CDE_CX2D; in Select()
5363 Opcode = HasAccum ? ARM::CDE_CX3DA : ARM::CDE_CX3D; in Select()
5525 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
5530 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
5549 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
5558 .Case("fpscr", ARM::VMRS) in tryReadRegister()
5559 .Case("fpexc", ARM::VMRS_FPEXC) in tryReadRegister()
5560 .Case("fpsid", ARM::VMRS_FPSID) in tryReadRegister()
5561 .Case("mvfr0", ARM::VMRS_MVFR0) in tryReadRegister()
5562 .Case("mvfr1", ARM::VMRS_MVFR1) in tryReadRegister()
5563 .Case("mvfr2", ARM::VMRS_MVFR2) in tryReadRegister()
5564 .Case("fpinst", ARM::VMRS_FPINST) in tryReadRegister()
5565 .Case("fpinst2", ARM::VMRS_FPINST2) in tryReadRegister()
5572 if (Opcode == ARM::VMRS_MVFR2 && !Subtarget->hasFPARMv8Base()) in tryReadRegister()
5594 N, CurDAG->getMachineNode(ARM::t2MRS_M, DL, MVT::i32, MVT::Other, Ops)); in tryReadRegister()
5603 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
5612 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
5639 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
5644 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
5664 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
5673 .Case("fpscr", ARM::VMSR) in tryWriteRegister()
5674 .Case("fpexc", ARM::VMSR_FPEXC) in tryWriteRegister()
5675 .Case("fpsid", ARM::VMSR_FPSID) in tryWriteRegister()
5676 .Case("fpinst", ARM::VMSR_FPINST) in tryWriteRegister()
5677 .Case("fpinst2", ARM::VMSR_FPINST2) in tryWriteRegister()
5704 ReplaceNode(N, CurDAG->getMachineNode(ARM::t2MSR_M, DL, MVT::Other, Ops)); in tryWriteRegister()
5716 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSR_AR : ARM::MSR, in tryWriteRegister()
5795 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID)) in tryInlineAsm()
5812 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5821 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
5823 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
5848 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass); in tryInlineAsm()
5864 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID); in tryInlineAsm()